ST STM32L4+ Series Reference Manual page 844

Digital filter for sigma delta modulators (DFSDM)
Figure 196. First conversion for Manchester coding (Manchester synchronization)
SITP = 2
SITP = 3
recovered clock
data from
modulator
CHEN
first conversion
start trigger
recovered data
CKABF[y]
External serial clock frequency measurement
The measuring of a channel serial clock input frequency provides a real data rate from an
external Σ∆ modulator, which is important for application purposes.
An external serial clock input frequency can be measured by a timer counting DFSDM
clocks (f
DFSDMCLK
clock after a conversion trigger (regular or injected) and finishes by last input data clock
before conversion ends (end of conversion flag is set). Each conversion duration (time
between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in
register DFSDM_FLTxCNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1).
The user can then compute the data rate according to the digital filter settings (FORD,
FOSR, IOSR, FAST). The external serial frequency measurement is stopped only if the filter
is bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in
DFSDM_FLTxCNVTIMR register).
In case of parallel data input
is the average input data rate during one conversion.
844/2301
0 0
? ?
) during one conversion duration. The counting starts at the first input data
(Section 28.4.6: Parallel data
RM0432 Rev 6
1 1
real start of first conversion
first data bit toggle - end of Manchester synchronization
1 1
clearing of CKABF[y] flag by software polling
inputs) the measured frequency
RM0432
0
0
MS30769V2