ST STM32L4+ Series Reference Manual page 297

RM0432
Bit 2 DMAMUX1SMEN: DMAMUX1 clock enable during Sleep and Stop modes.
Bit 1 DMA2SMEN: DMA2 clocks enable during Sleep and Stop modes
Bit 0 DMA1SMEN: DMA1 clocks enable during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
6.4.23 AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
Address offset: 0x6C
Reset value: 0x0057 77FF
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
PKASM DCMIS ADCS OTGFS
EN MEN MEN SMEN
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 SDMMC2SMEN: SDMMC2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SDMMC2 clocks disabled by the clock gating
1: SDMMC2 clocks enabled by the clock gating
Bit 22 SDMMC1SMEN: SDMMC1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SDMMC1 clocks disabled by the clock gating
1: SDMMC1 clocks enabled by the clock gating
Bit 21 Reserved, must be kept at reset value.
Bit 20 OSPIMSMEN: OctoSPI IO manager clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OCTOSPIM clocks disabled by the clock gating
1: OCTOSPIM clocks enabled by the clock gating
Bit 19 Reserved, must be kept at reset value.
Set and cleared by software.
0: DMAMUX1 clocks disabled by the clock gating
1: DMAMUX1 clocks enabled by the clock gating
Set and cleared by software during Sleep mode.
0: DMA2 clocks disabled by the clock gating
1: DMA2 clocks enabled by the clock gating
Set and cleared by software.
0: DMA1 clocks disabled by the clock gating
1: DMA1 clocks enabled by the clock gating
28 27 26 25
Res. Res. Res.
12 11 10 9
SRAM3 SRAM2
Res.
SMEN SMEN
rw rw rw
(1)
(1)
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
24 23 22
SDMM SDMM
Res. C2SME C1SME
N N
rw rw
8 7 6
GPIOIS GPIOH GPIOG GPIOF
MEN SMEN SMEN SMEN
rw rw rw
(1)
(1)
during Sleep and Stop modes
(1)
(1)
during Sleep and Stop modes
(1)
(1)
RM0432 Rev 6
Reset and clock control (RCC)
during Sleep and Stop modes
during Sleep and Stop modes
21 20 19 18
OSPIM RNGS
Res. Res.
SMEN MEN
rw rw
5 4 3 2
GPIOE GPIOD GPIOC
SMEN SMEN SMEN
rw rw rw rw
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
17 16
HASHS AESSM
MEN EN
rw rw
1 0
GPIOB GPIOA
SMEN SMEN
rw rw
297/2301
320