ST STM32L4+ Series Reference Manual page 456

Chrom-GRC™ (GFXMMU)
0xFF:FFFF
0xDF:FFFF
0xC0:0000
0xAF:FFFF
0x80:0000
0x6F:FFFF
0x40:0000
0x2F:FFFF
0x00:0000
The buffer can not overflow the 8 MByte boundary of the zone defined by its base address.
In case of overflow, the buffer x overflow flag (BxOF) of the graphic MMU status register
(GFXMMU_SR) is set and an interrupt is generated if the buffer x overflow interrupt enable
(BxOIE) bit of the graphic MMU configuration register (GFXMMU_CR) is set.
Virtual buffer application use case
As the physical locations are independently configurable, the four virtual buffers can be
physically mapped to non continuous locations. This would allow for example to have the
four buffers mapped on to four different SDRAM banks and avoid extra precharge cycles
accessing the SDRAM.
As a consequence, one buffer shall be used by the CPU/ChromART
calculation while an other one shall be used by the LTDC.
The two remaining buffers can be used as a graphical library requiring extra drawing
buffers.
14.3.2 MMU architecture
The MMU block is responsible of the address resolution. It receives the 24-bit address and
returns the physical 23-bit address and a valid signals to indicate the address is physically
mapped or not. The MMU also checks overflow of a area boundary.
456/2301
Figure 40. Virtual buffer and physical buffer memory map
Virtual buffer
Virtual buffer 3
(3/4 Mbyte)
Virtual buffer 2
(3/4 Mbyte)
Virtual buffer 1
(3/4 Mbyte)
Virtual buffer 0
(3/4 Mbyte)
RM0432 Rev 6
Physical buffer
pBuffer3
0xYY:Y000
0xXX00:0000
pBuffer2
0xYY:Y000
0xXX00:0000
pBuffer1
0xYY:Y000
0xXX00:0000
pBuffer0
0xYY:Y000
0xXX00:0000
RM0432
Physical buffer 3 offset
Physical buffer 3 base address
Physical buffer 2 offset
Physical buffer 2 base address
Physical buffer 1 offset
Physical buffer 1 base address
Physical buffer 0 offset
Physical buffer 0 base address
MSv43801V2
®
for frame buffer