ST STM32L4+ Series Reference Manual page 438

Chrom-ART Accelerator controller (DMA2D)
13.5.8 DMA2D foreground PFC control register (DMA2D_FGPFCCR)
Address offset: 0x001C
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:24 ALPHA[7:0]: Alpha value
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RBS: Red Blue Swap
Bit 20 AI: AI: Alpha Inverted
Bits 19:18 Reserved, must be kept at reset value.
Bits 17:16 AM[1:0]: Alpha mode
Bits 15:8 CS[7:0]: CLUT size
Bits 7:6 Reserved, must be kept at reset value.
438/2301
28 27 26 25
ALPHA[7:0]
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12 11 10 9
CS[7:0]
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These bits define a fixed alpha channel value which can replace the original alpha value
or be multiplied by the original alpha value according to the alpha mode selected
through the AM[1:0] bits.
These bits can only be written when data transfers are disabled. Once a transfer has
started, they become read-only.
This bit allows to swap the R & B to support BGR or ABGR color formats. Once the
transfer has started, this bit is read-only.
0: Regular mode (RGB or ARGB)
1: Swap mode (BGR or ABGR)
This bit inverts the alpha value. Once the transfer has started, this bit is read-only.
0: Regular alpha
1: Inverted alpha
These bits select the alpha channel value to be used for the foreground image. They
can only be written data the transfer are disabled. Once the transfer has started, they
become read-only.
00: No modification of the foreground image alpha channel value
01: Replace original foreground image alpha channel value by ALPHA[7:0]
10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied
with original alpha channel value
other configurations are meaningless
These bits define the size of the CLUT used for the foreground image. Once the CLUT
transfer has started, this field is read-only.
The number of CLUT entries is equal to CS[7:0] + 1.
24 23 22
Res. Res.
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8 7 6
Res. Res. START
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RM0432 Rev 6
21 20 19 18
RBS AI Res. Res.
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5 4 3 2
CCM
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RM0432
17 16
AM[1:0]
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1 0
CM[3:0]
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