ST STM32L4+ Series Reference Manual page 195

RM0432
1. If V
DDIO2
a)
b)
c)
d)
2. Set the IOSV bit in the
power isolation.
The following sequence must be done before using any of these analog peripherals: analog
to digital converters, digital to analog converters, comparators, operational amplifiers,
voltage reference buffer:
1. If V
DDA
a)
b)
c)
d)
2. Enable the analog peripheral, which automatically removes the V
5.3 Low-power modes
By default, the microcontroller is in Run mode after a system or a power Reset. Several low-
power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.
The device features seven low-power modes:
•
Sleep mode: CPU clock off, all peripherals including Cortex
as NVIC, SysTick, etc. can run and wake up the CPU when an interrupt or an event
occurs. Refer to
•
Low-power run mode: This mode is achieved when the system clock frequency is
reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The
regulator is in low-power mode to minimize the regulator's operating current. Refer to
Section 5.3.2: Low-power run mode (LP
•
Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex
M4 is off. Refer to
•
Stop 0, Stop 1 and Stop 2 modes: SRAM1, SRAM2, SRAM3 and all registers content
are retained. All clocks in the V
and the HSE are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop
mode to detect their wakeup condition.
In Stop 2 mode, most of the V
reduce the current consumption during Stop 2, it is possible to switch OFF the SRAM3:
–
is independent from V
Enable the PVM2 by setting PVME2 bit in the
(PWR_CR2).
Wait for the PVM2 wakeup time
Wait until PVMO2 bit is cleared in the
Optional: Disable the PVM2 for consumption saving.
Power control register 2 (PWR_CR2)
is independent from V
Enable the PVM3 (or PVM4) by setting PVME3 (or PVME4) bit in the
control register 2 (PWR_CR2).
Wait for the PVM3 (or PVM4) wakeup time
Wait until PVMO3 (or PVMO4) bit is cleared in the
(PWR_SR2).
Optional: Disable the PVM3 (or PVM4) for consumption saving.
Section 5.3.4: Sleep
Section 5.3.5: Low-power sleep mode (LP
Stop 2 mode with SRAM3 content lost when the RRSTP bit is cleared in
:
DD
Power status register 2
:
DD
mode.
run).
domain are stopped, the PLL, the MSI, the HSI16
CORE
domain is put in a lower leakage mode.To further
CORE
RM0432 Rev 6
Power control (PWR)
Power control register 2
(PWR_SR2).
to remove the V
Power status register 2
isolation.
DDA
®
-M4 core peripherals such
sleep).
DDIO2
Power
®
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