ST STM32L4+ Series Reference Manual page 423

RM0432
13.3.7 DMA2D output PFC
The output PFC performs the pixel format conversion from 32 bits to the output format
defined in the CM[2:0] field of the DMA2D output pixel format converter configuration
register (DMA2D_OPFCCR).
The supported output formats are given in
000
001
010
011
100
Note: To support the alternate format, the calculated alpha value is inverted setting the AI bit of the
DMA2D_OPFCCR registers. This applies also to the Alpha value used in the
DMA2D_OCOLR.
The R and B fields can also be swapped setting the RBS bit of the DMA2D_OPFCCR
registers. This applies also to the RGB order used in the DMA2D_OCOLR.
13.3.8 DMA2D output FIFO
The output FIFO programs the pixels according to the color format defined in the output
PFC.
The destination area is defined through a set of control registers:
•
DMA2D output memory address register (DMA2D_OMAR)
•
DMA2D output offset register (DMA2D_OOR)
•
DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled
by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains
a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the
DMA2D_OPFCCR register.
The data are stored into the memory in the order defined in
Color Mode
ARGB8888
RGB888
RGB565
Table 68. Supported color mode in output
CM[2:0]
Table 69. Data order in memory
@ + 3
A [7:0]
0
B [7:0]
1
G [7:0]
2
R [7:0]
3
R [4:0]G [5:3] G
1 1
RM0432 Rev 6
Chrom-ART Accelerator controller (DMA2D)
Table 68: Supported color mode in output
@ + 2
R [7:0]
0
R [7:0]
0
B [7:0]
2
G [7:0]
3
[2:0]B [4:0] R
1 1 0
Color mode
ARGB8888
RGB888
RGB565
ARGB1555
ARGB4444
Table 69: Data order in memory
@ + 1
G [7:0]
0
G [7:0]
0
R [7:0]
1
B [7:0]
3
[4:0]G [5:3] G [2:0]B
0 0
@ + 0
B [7:0]
0
B [7:0]
0
G [7:0]
1
R [7:0]
2
[4:0]
0
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