ST STM32L4+ Series Reference Manual page 1090

True random number generator (RNG) applied to STM32L4P5xx and STM32L4Q5xx only RM0432
Bit 12 NISTC: Non NIST compliant
Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while
CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK=1.
Bits 11:8 RNG_CONFIG3[3:0]: RNG configuration 3
Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details.
If NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG.
Bit 7 Reserved, must be kept at reset value.
Bit 6 Reserved, must be kept at reset value.
Bit 5 CED: Clock error detection
The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is enabled,
i.e. to enable or disable CED the RNG must be disabled.
Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while
CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK=1.
Bit 4 Reserved, must be kept at reset value.
Bit 3 IE: Interrupt Enable
Bit 2 RNGEN: True random number generator enable
Bits 1:0 Reserved, must be kept at reset value.
1090/2301
0: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output
two conditioning loops are performed and 256 bits of noise source are used.
1: Custom values for NIST compliant RNG. See
validation for
proposed configuration.
0: Clock error detection is enable
1: Clock error detection is disable
0: RNG Interrupt is disabled
1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY='1', SEIS='1' or
CEIS=1 in the RNG_SR register.
0: True random number generator is disabled. Analog noise sources are powered off and
logic clocked by the RNG clock is gated.
1: True random number generator is enabled.
Section 33.6: RNG entropy source
RM0432 Rev 6