ST STM32L4+ Series Reference Manual page 1072

True random number generator (RNG) applied to STM32L4Rxxx and STM32L4Sxxx only RM0432
32.4 RNG interrupts
In the RNG an interrupt can be produced on the following events:
•
Data ready flag
• Seed error, see
•
Clock error, see
Dedicated interrupt enable control bits are available as shown in
Interrupt acronym
RNG
The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note: Interrupts are generated only when RNG is enabled.
32.5 RNG processing time
The conditioning stage can produce four 32-bit random numbers every 16x
cycles, if the value is higher than 213 cycles (213 cycles otherwise).
More time is needed for the first set of random numbers after the device exits reset (see
Section 32.3.4: RNG
data is first available after either:
•
128 RNG clock cycles + 426 AHB cycles, if f
•
192 RNG clock cycles + 213 AHB cycles, if f
With f
threshold
1072/2301
Section 32.3.7: Error management
Section 32.3.7: Error management
Table 218. RNG interrupt requests
Interrupt event Event flag
Data ready flag
Seed error flag
Clock error flag
initialization). Indeed, after enabling the RNG for the first time, random
= (213 x f )/ 64
RNG
Enable control bit
DRDY IE
SEIS IE
CEIS IE
< f
AHB
≥ f
AHB
RM0432 Rev 6
Table 218.
Interrupt clear method
None (automatic)
Write 0 to SEIS
Write 0 to CEIS
f
AHB
------------
f
RNG
threshold
threshold
clock