ST STM32L4+ Series Reference Manual page 150

Embedded Flash memory (FLASH)
3.7 FLASH registers
3.7.1 Flash access control register (FLASH_ACR)
Address offset: 0x00
Reset value: 0x0000 0600
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
SLEEP RUN_
Res. DCRST ICRST
_PD
PD
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--
Bits 31:15 Reserved, must be kept at reset value.
150/2301
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
DCEN ICEN
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Bit 14 SLEEP_PD: Flash Power-down mode during Sleep or Low-power sleep mode
This bit determines whether the Flash memory is in Power-down mode or idle
mode when the device is in Sleep or Low-power sleep mode.
0: Flash in idle mode during Sleep and Low-power sleep modes
1: Flash in Power-down mode during Sleep and Low-power sleep modes
Caution: The Flash must not be put in power-down while a program or an erase
operation is on-going.
Bit 13 RUN_PD: Flash Power-down mode during Run or Low-power run mode
This bit is write-protected with FLASH_PDKEYR.
This bit determines whether the Flash memory is in Power-down mode or idle
mode when the device is in Run or Low-power run mode. The Flash memory can
be put in Power-down mode only when the code is executed from RAM. The
Flash must not be accessed when RUN_PD is set.
0: Flash in idle mode
1: Flash in Power-down mode
Caution: The Flash must not be put in power-down while a program or an erase
operation is on-going.
Bit 12 DCRST: Data cache reset
0: Data cache is not reset
1: Data cache is reset
This bit can be written only when the data cache is disabled.
Bit 11 ICRST: Instruction cache reset
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the instruction cache is disabled.
Bit 10 DCEN: Data cache enable
0: Data cache is disabled
1: Data cache is enabled
24 23 22
Res. Res. Res.
8 7 6
PRFTE
Res. Res.
N
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RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. LATENCY [3:0
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RM0432
17 16
Res. Res.
1 0
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