ST STM32L4+ Series Reference Manual page 447

RM0432
Bits 11:8 RED[3:0]: Red value in ARGB4444 mode
Bits 7:4 GREEN[3:0]: Green value in ARGB4444 mode
Bits 3:0 BLUE[3:0]: Blue value in ARGB4444 mode
13.5.16 DMA2D output memory address register (DMA2D_OMAR)
Address offset: 0x003C
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 MA[31:0]: Memory Address
13.5.17 DMA2D output offset register (DMA2D_OOR)
Address offset: 0x0040
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
These bits define the red value of the output image. These bits can only be written when
data transfers are disabled. Once the transfer has started, they are read-only.
These bits define the green value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
These bits define the blue value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Address of the data used for the output FIFO. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
Chrom-ART Accelerator controller (DMA2D)
24 23 22
MA[31:16]
rw rw rw
8 7 6
MA[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
LO[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
rw rw
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