ST STM32L4+ Series Reference Manual page 631

RM0432
21.4.16 ADC timing
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
T
CONV
T
CONV
ADC state
Analog channel
Internal S/H
ADSTART
EOSMP
EOC
ADC_DR
1. T
SMPL
2. T depends on RES[2:0].
SAR
21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)
The software can decide to stop regular conversions ongoing by setting ADSTP=1 and
injected conversions ongoing by setting JADSTP=1.
Stopping conversions will reset the ongoing ADC operation. Then the ADC can be
reconfigured (ex: changing the channel selection or the trigger) ready for a new operation.
Note that it is possible to stop injected conversions while regular conversions are still
operating and vice-versa. This allows, for instance, re-configuration of the injected
conversion sequence and triggers while regular conversions are still operating (and vice-
versa).
When the ADSTP bit is set by software, any ongoing regular conversion is aborted with
partial result discarded (ADC_DR register is not updated with the current conversion).
When the JADSTP bit is set by software, any ongoing injected conversion is aborted with
partial result discarded (ADC_JDRy register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that relaunching the ADC would
restart a new sequence).
Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or
JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the
software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC
is completely stopped.
= T + T = [2.5
SMPL SAR
83.33
= T + T =
SMPL SAR
Figure 96. Analog to digital conversion time
RDY Sampling Ch(N)
Ch(N)
Sample AIN(N)
t
Set
by S/W
depends on SMP[2:0].
+ 12.5 ] x T
|min |12bit ADC_CLK
416.67
ns + ns
|min |12bit
(1)
SMPL
Set
Cleared
by H/W
by S/W
Data N-1
Indicative timings
RM0432 Rev 6
Analog-to-digital converters (ADC)
= 500.0 ns (for F
ADC_CLK
Converting Ch(N)
Hold AIN(N)
t (2)
SAR
Set
by H/W
= 30 MHz)
Sampling Ch(N+1)
Ch(N+1)
Sample AIN(N+1)
Cleared
by S/W
Data N
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