ST STM32L4+ Series Reference Manual page 552

Flexible static memory controller (FSMC)
Bits 7:0 ATTSET[7:0]: Attribute memory setup time
ECC result registers (FMC_ECCR)
Address offset: 0x94
Reset value: 0x0000 0000
This register contain the current error correction code value computed by the ECC
computation modules of the FMC NAND controller. When the CPU reads the data from a
NAND Flash memory page at the correct address (refer to
the error correction code (ECC) in NAND Flash
NAND Flash memory are processed automatically by the ECC computation module. When
X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU
must read the computed ECC value from the FMC_ECC registers. It then verifies if these
computed parity data are the same as the parity value recorded in the spare area, to
determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register
should be cleared after being read by setting the ECCEN bit to 0. To compute a new data
block, the ECCEN bit must be set to 1.
31 30 29
r r r
15 14 13
r r r
Bits 31:0 ECC[31:0]: ECC result
ECCPS[2:0]
552/2301
Defines the number of HCLK (+1) clock cycles to set up address before the command
assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on
socket:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
28 27 26 25
r r r r
12 11 10 9
r r r r
This field contains the value computed by the ECC computation logic.
the contents of these bitfields.
Table 117. ECC result relevant bits
000
001
010
011
100
101
memory), the data read/written from/to the
24 23 22
ECC[31:16]
r r r
8 7 6
ECC[15:0]
r r r
Page size in bytes
256
512
1024
2048
4096
8192
RM0432 Rev 6
Section 18.8.6: Computation of
21 20 19 18
r r r r
5 4 3 2
r r r r
Table 117
ECC bits
ECC[21:0]
ECC[23:0]
ECC[25:0]
ECC[27:0]
ECC[29:0]
ECC[31:0]
RM0432
17 16
r r
1 0
r r
describes