ST STM32L4+ Series Reference Manual page 618

Analog-to-digital converters (ADC)
RCC
(Reset and
clock
controller)
Clock ratio constraint between ADC clock and AHB clock
There are generally no constraints to be respected for the ratio between the ADC clock and
the AHB clock except if some injected channels are programmed. In this case, it is
mandatory to respect the following ratio:
• F
HCLK
•
F
HCLK
with lower resolutions)
•
F
HCLK
618/2301
Figure 89. ADC clock scheme
ADC1 and ADC2
HCLK
Bits CKMODE[1:0]
/1, 2, 4, 6, 8, 10,
ADC12_CK
12, 16, 32, 64,
128, 256
>= F / 4 if the resolution of all channels are 12-bit or 10-bit
ADC
>= F / 3 if there are some channels with resolutions equal to 8-bit (and none
ADC
>= F / 2 if there are some channels with resolutions equal to 6-bit
ADC
RM0432 Rev 6
AHB interface
of ADCx_CCR
/1 or /2 or /4
Others
00
Bits PREC[3:0] Bits CKMODE[1:0]
of ADCx_CCR of ADCx_CCR
RM0432
Analog ADC1
(master)
Analog ADC2
(slave)
MSv50635V1