ST STM32L4+ Series Reference Manual page 655

RM0432
Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG of the ADC_CFGR register in single ADC mode, or with bit
DMACFG of the ADC_CCR register in dual ADC mode:
•
DMA one shot mode (DMACFG=0).
This mode is suitable when the DMA is programmed to transfer a fixed number of data.
•
DMA circular mode (DMACFG=1)
This mode is suitable when programming the DMA in circular mode.
DMA one shot mode (DMACFG=0)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available and stops generating DMA requests once the DMA has reached the last DMA
transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion
has been started again.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
•
The content of the ADC data register is frozen.
•
Any ongoing conversion is aborted with partial result discarded.
•
No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
•
Scan sequence is stopped and reset.
•
The DMA is stopped.
DMA circular mode (DMACFG=1)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available in the data register, even if the DMA has reached the last DMA transfer. This
allows configuring the DMA in circular mode to handle a continuous analog input data
stream.
21.4.27 Managing conversions using the DFSDM
The ADC conversion results can be transferred directly to the Digital filter for sigma delta
modulators (DFSDM).
In this case, the DFSDMCFG bit must be set to 1 and DMAEN bit must be cleared to 0.
The ADC transfers all the 16 bits of the regular data register to the DFSDM and resets the
EOC flag once the transfer is complete.
Section : ADC overrun (OVR, OVRMOD)).
RM0432 Rev 6
Analog-to-digital converters (ADC)
655/2301
724