ST STM32L4+ Series Reference Manual page 563

RM0432
Quad-SPI mode
In Quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3
signals.
The different phases can each be configured separately to use the Quad-SPI mode by
setting to 011 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase configured in Quad-SPI mode:
•
IO0/IO1/IO2/IO3 are all are at high-impedance (input) during the data phase for the
read operations, and outputs in all other cases.
• IO4/IO5/IO6/IO7 are in output mode and forced to 0.
In the dummy phase when DMODE[2:0] = 011, IO0/IO1/IO2/IO3 are all high-impedance.
IO2 and IO3 are used only in Quad-SPI mode. If none of the phases are configured to use
the Quad-SPI mode, then the pins corresponding to IO2 and IO3 can be used for other
functions even while the OCTOSPI is active.
Octo-SPI mode
In regular Octo-SPI mode, the eight bits are sent/received simultaneously over the IO[0:7]
signals.
The different phases can each be configured separately to use the Octo-SPI mode by
setting to 100 the IMODE/ADMODE/ABMODE/DMODE fields (in OCTOSPI_CCR and
OCTOSPI_WCCR).
In each phase that is configured in Octal mode, IO[0:7] are all at high-impedance (input)
during the data phase for read operations, and outputs in all other cases.
In the dummy phase when DMODE[2:0] = 100, IO[0:7] are all high-impedance.
IO[4:7] are used only in Octo-SPI mode. If none of the phases are configured to use
Octo-SPI mode, then the pins corresponding to IO[4:7] can be used for other functions even
while the OCTOSPI is active.
Single-data rate (SDR) mode
By default, all the phases operate in Single-data rate (SDR) mode.
In SDR mode, when the OCTOSPI is driving the IO0/SO, IO1, IO2, IO3, IO4, IO5, IO6 and
IO7 signals, these signals transition only with the falling edge of CLK.
When receiving data in SDR mode, the OCTOSPI assumes that the external devices also
send the data using CLK falling edge. By default (when SSHIFT = 0 in OCTOSPI_TCR), the
signals are sampled using the following (rising) edge of CLK.
CS#
CLK
IO[7:0]
Figure 73. SDR write command in Octo-SPI mode
02h FDh A[31:24] A[23:16]
RM0432 Rev 6
Octo-SPI interface (OCTOSPI)
A[15:8] A[7:0] D0 D1
example.
D254 D255
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