ST STM32L4+ Series Reference Manual page 877

RM0432
Bits 31:8 AWLT[23:0]: Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define
the 16-bit threshold as compared with the analog watchdog filter output (because data coming
from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
28.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR)
Address offset: 0x128 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 AWHTF[7:0]: Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
Bits 7:0 AWLTF[7:0]: Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.
Note: All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0.
28 27 26 25
Res. Res. Res.
12 11 10 9
AWHTF[7:0]
r r r r
Digital filter for sigma delta modulators (DFSDM)
24 23 22
Res. Res. Res.
8 7 6
r r r
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
AWLTF[7:0]
r r r r
17 16
Res. Res.
1 0
r r
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