ST STM32L4+ Series Reference Manual page 859

RM0432
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Short-circuit detector interrupt:
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Channel clock absence interrupt:
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Interrupt event
End of injected conversion
End of regular conversion
Injected data overrun
Regular data overrun
Analog watchdog
short-circuit detector
Channel clock absence
occurred when converted data (output data or data from analog watchdog filter -
according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses
over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR
registers
enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels
AWDCH[7:0])
indicated in AWDF bit in DFSDM_FLTxISR register
separate indication of high or low analog watchdog threshold error by AWHTF[7:0]
and AWLTF[7:0] fields in DFSDM_FLTxAWSR register
cleared by writing '1' into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits
in DFSDM_FLTxAWCFR register
occurred when the number of stable data crosses over thresholds in
DFSDM_CHyAWSCDR register
enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by
SCDEN bi tin DFSDM_CHyCFGR1 register)
indicated in SCDF[7:0] bits in DFSDM_FLTxISR register (which also reports the
channel on which the short-circuit detector event occurred)
cleared by writing '1' into the corresponding CLRSCDF[7:0] bit in
DFSDM_FLTxICR register
occurred when there is clock absence on CKINy pin (see
in Section 28.4.4: Serial channel
enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by
CKABEN bit in DFSDM_CHyCFGR1 register)
indicated in CKABF[y] bit in DFSDM_FLTxISR register
cleared by writing '1' into CLRCKABF[y] bit in DFSDM_FLTxICR register
Table 190. DFSDM interrupt requests
Event flag
JEOCF
REOCF
JOVRF
ROVRF
AWDF,
AWHTF[7:0],
AWLTF[7:0]
SCDF[7:0]
CKABF[7:0]
Digital filter for sigma delta modulators (DFSDM)
transceivers)
Event/Interrupt clearing
reading DFSDM_FLTxJDATAR
reading DFSDM_FLTxRDATAR REOCIE
writing CLRJOVRF = 1
writing CLRROVRF = 1
writing CLRAWHTF[7:0] = 1
writing CLRAWLTF[7:0] = 1
writing CLRSCDF[7:0] = 1
writing CLRCKABF[7:0] = 1
RM0432 Rev 6
Clock absence detection
Interrupt enable
method
JEOCIE
JOVRIE
ROVRIE
AWDIE,
(AWDCH[7:0])
SCDIE,
(SCDEN)
CKABIE,
(CKABEN)
control bit
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