ST STM32F101 Series Reference Manual
Advanced arm-based 32-bit mcus
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Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F101xx and STM32F103xx microcontroller memory and peripherals.
The STM32F101xx and STM32F103xx will be referred to as STM32F10xxx throughout the
document.
The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
STM32F101xx and STM32F103xx datasheets.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical
Reference Manual.
Related documents
Available from www.arm.com:
Cortex™-M3 Technical Reference Manual
Available from www.st.com:
STM32F101xx STM32F103xx datasheets
STM32F10xxx Flash programming manual
November 2007
Reference manual
STM32F101xx and STM32F103xx
advanced ARM-based 32-bit MCUs
Rev 2
RM0008
1/501
www.st.com
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Table of Contents
Related Manuals for ST STM32F101 Series
Summary of Contents for ST STM32F101 Series
- Page 1 STM32F10xxx Flash programming manual. For information on the ARM Cortex™-M3 core, please refer to the Cortex™-M3 Technical Reference Manual. Related documents Available from www.arm.com: Cortex™-M3 Technical Reference Manual Available from www.st.com: STM32F101xx STM32F103xx datasheets STM32F10xxx Flash programming manual November 2007 Rev 2 1/501...
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Page 2: Table Of Contents
Contents RM0008 Contents Documentation conventions ....... . . 23 List of abbreviations for registers ....... 23 Memory and bus architecture . - Page 3 RM0008 Contents Reset and clock control (RCC) ....... . 47 Reset .
- Page 4 Contents RM0008 5.1.6 GPIO locking mechanism ........79 5.1.7 Input configuration .
- Page 5 RM0008 Contents External interrupt/event controller (EXTI) ......101 6.2.1 Main features ..........101 6.2.2 Block diagram .
- Page 6 Contents RM0008 RTC register description ........124 8.4.1 RTC control register High (RTC_CRH) .
- Page 7 RM0008 Contents 11.3 Functional description ........143 11.4 How to program the watchdog timeout .
- Page 8 Contents RM0008 12.5.1 Control register 1 (TIM1_CR1) ......188 12.5.2 Control register 2 (TIM1_CR2) ......190 12.5.3 Slave mode control register (TIM1_SMCR) .
- Page 9 RM0008 Contents 13.4.11 Clearing the OCxREF signal on an external event ....238 13.4.12 Encoder interface mode ........239 13.4.13 Timer input XOR function .
- Page 10 Contents RM0008 14.4 Operating modes ......... . 276 14.4.1 Initialization mode .
- Page 11 RM0008 Contents 15.5 Interrupt requests ......... . 333 15.6 C debug mode .
- Page 12 Contents RM0008 16.10.2 Regular simultaneous mode ....... . 360 16.10.3 Fast interleaved mode ........361 16.10.4 Slow interleaved mode .
- Page 13 RM0008 Contents 17.5.3 Double-buffered endpoints ........392 17.5.4 Isochronous transfers .
- Page 14 Contents RM0008 19.3 General description ........431 19.3.1 Block diagram .
- Page 15 RM0008 Contents 20.5 STM32F10xxx JTAG TAP connection ......473 20.6 ID codes and locking mechanism ......474 20.6.1 MCU device ID code .
- Page 16 Contents RM0008 20.16.10 Example of configuration ........493 20.17 DBG register map .
- Page 17 RM0008 List of tables List of tables Table 1. Register boundary addresses ..........27 Table 2.
- Page 18 List of tables RM0008 Table 49. Analog watchdog channel selection ......... 351 Table 50.
- Page 19 RM0008 List of figures List of figures Figure 1. System architecture ............24 Figure 2.
- Page 20 List of figures RM0008 Figure 49. External trigger input block ..........162 Figure 50.
- Page 21 RM0008 List of figures Figure 101. PWM input mode timing........... 231 Figure 102.
- Page 22 List of figures RM0008 Figure 153. Alternate trigger: injected channel group of each ADC......362 Figure 154.
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Page 23: Documentation Conventions
RM0008 Documentation conventions Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. -
Page 24: Memory And Bus Architecture
Memory and bus architecture RM0008 Memory and bus architecture System architecture The main system consists of: Four masters: – Cortex™-M3 core ICode bus (I-bus), DCode bus (D-bus), and System bus (S-bus) – GP-DMA (General Purpose DMA) Three slaves: – Internal SRAM –... -
Page 25: Memory Organization
RM0008 Memory and bus architecture DMA bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals. BusMatrix The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. -
Page 26: Memory Map
Memory and bus architecture RM0008 Memory map Figure 2. Memory map APB memory space 0xFFFF FFFF reserved 0xE010 0000 reserved Addressable memory space 0x6000 0000 4 Gbytes reserved 4 Kb 0x4002 3400 0xFFFF FFFF reserved 4 Kb 0x4002 2400 0xFFFF F000 Flash memory Interface 1 Kb 0x4002 2000... -
Page 27: Peripheral Memory Map
RM0008 Memory and bus architecture 2.3.1 Peripheral memory map Table 1. Register boundary addresses Boundary address Peripheral Register map 0x4002 2400 - 0x4002 3FFF Reserved 0x4002 2000 - 0x4002 23FF Flash memory interface 0x4002 1400 - 0x4002 1FFF Reserved 0x4002 1000 - 0x4002 13FF Reset and Clock control RCC Section 4.4 on page 74 0x4002 0400 - 0x4002 0FFF Reserved... -
Page 28: Embedded Sram
Memory and bus architecture RM0008 Table 1. Register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 8000 - 0x4000 77FF Reserved 0x4000 7000 - 0x4000 73FF Power control PWR Section 3.5 on page 46 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 9.6 on page 136 0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF... -
Page 29: Embedded Flash Memory
RM0008 Memory and bus architecture A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. -
Page 30: Table 2. Flash Module Organization
Memory and bus architecture RM0008 Table 2. Flash module organization Block Name Addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte Page 3 0x0800 0C00 - 0x0800 0FFF... - Page 31 RM0008 Memory and bus architecture Reading Flash memory Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus. Read accesses can be performed with the following configuration options: Latency: number of wait states for a read operation programmed on-the-fly Prefetch buffer (2 x 64-bit blocks): it is enabled after reset;...
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Page 32: Boot Configuration
0x0000 0000. Embedded boot loader The embedded boot loader is used to reprogram the Flash memory using the USART1 serial interface. This program is located in the SystemMemory and is programmed by ST during production. 32/501... -
Page 33: Power Control (Pwr)
RM0008 Power control (PWR) Power control (PWR) Power supplies The device requires a 2.0-to-3.6 V operating voltage supply (V ). An embedded regulator is used to supply the internal 1.8 V digital power. The real-time clock (RTC) and backup registers can be powered from the V voltage when the main V supply is powered off. -
Page 34: Battery Backup Domain
Power control (PWR) RM0008 On 100-pin packages To ensure a better accuracy on low voltage inputs, the user can connect a separate external reference voltage ADC input on V and V . The voltage on V can range from REF+ REF- REF+ 2.4 V to V... -
Page 35: Voltage Regulator
RM0008 Power control (PWR) 3.1.3 Voltage regulator The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals). -
Page 36: Figure 5. Pvd Thresholds
Power control (PWR) RM0008 rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. Figure 5. PVD thresholds 100 mV PVD threshold hysteresis PVD output 36/501... -
Page 37: Low-Power Modes
RM0008 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. -
Page 38: Sleep Mode
Power control (PWR) RM0008 To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. Peripheral clock gating is controlled by the AHB Peripheral Clock enable register (RCC_AHBENR), APB1 Peripheral Clock enable register (RCC_APB1ENR) APB2 Peripheral Clock enable register (RCC_APB2ENR). -
Page 39: Stop Mode
RM0008 Power control (PWR) Table 6. Sleep-on-exit Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 1 Refer to the Cortex™-M3 System Control register. Mode exit Interrupt: refer to Table 27: Vector table. -
Page 40: Standby Mode
Power control (PWR) RM0008 Table 7. Stop mode Stop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex™-M3 System Control register – Clear PDDS bit in Power Control register (PWR_CR) – Select the voltage regulator mode by configuring LPDS bit in PWR_CR Mode entry Note: To enter Stop mode, all EXTI Line pending bits (in Pending register... -
Page 41: Auto Wakeup (Awu) From Low-Power Mode
RM0008 Power control (PWR) Exiting Standby mode The microcontroller exits Standby mode when an external Reset (NRST pin), IWDG Reset, a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after wakeup from Standby except for Power control/status register (PWR_CSR). - Page 42 Power control (PWR) RM0008 alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR): Low-power 32.768 kHz external crystal oscillator (LSE OSC). This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions) Low-power internal RC Oscillator (LSI RC) This clock source has the advantage of saving the cost of the 32.768 kHz crystal.
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Page 43: Power Control Registers
RM0008 Power control (PWR) Power control registers 3.4.1 Power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) Reserved Res. Reserved PLS[2:0] PVDE CSBF CWUF PDDS LPDS rc_w1 rc_w1 Bits 31:9 Reserved, always read as 0. Bit 8 DBP: Disable Backup Domain write protection. - Page 44 Power control (PWR) RM0008 Bit 1 PDDS: Power Down Deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters Deepsleep.
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Page 45: Power Control/Status Register (Pwr_Csr)
RM0008 Power control (PWR) 3.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. Reserved Res. Reserved Reserved EWUP PVDO... -
Page 46: Pwr Register Map
Power control (PWR) RM0008 PWR register map The following table summarizes the PWR registers. Table 9. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 000h Reserved Reset value PWR_CSR 004h Reserved Reserved Reset value Refer to Table 1 on page 27 for the register boundary addresses. -
Page 47: Reset And Clock Control (Rcc)
RM0008 Reset and clock control (RCC) Reset and clock control (RCC) Reset There are three types of reset, defined as system Reset, power Reset and backup domain Reset. 4.1.1 System Reset A system Reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 3.). -
Page 48: Power Reset
Reset and clock control (RCC) RM0008 4.1.2 Power reset A power Reset is generated when one of the following events occurs: Power On/Power down Reset (POR/PDR Reset) When exiting Standby mode A power Reset sets all registers to their reset values except the Backup domain (see Figure These sources act on the RESET pin and it is always kept low during the delay phase. -
Page 49: Figure 7. Clock Tree
RM0008 Reset and clock control (RCC) Each clock source can be switched on or off independently when it is not used, to optimize power consumption. Figure 7. Clock tree 8 MHz HSI RC USBCLK 48 MHz to USB interface Prescaler /1, 1.5 HCLK 72 MHz max... -
Page 50: Hse Clock
Reset and clock control (RCC) RM0008 The timer clock frequencies are twice the frequency of the APB domain which they are connected to. Nevertheless, if the APB prescaler is 1, the clock frequency of the timer is the same as the frequency of the APB domain which it is connected to. FCLK acts as Cortex™-M3 free running clock. -
Page 51: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After Reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the... -
Page 52: Lse Clock
Reset and clock control (RCC) RM0008 If the USB interface is used in the application, the PLL must be programmed to output 48 or 72 MHz. This is needed to provide a 48 MHz USBCLK. 4.2.4 LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. -
Page 53: Clock Security System (Css)
RM0008 Reset and clock control (RCC) 4.2.7 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System... -
Page 54: Rcc Register Description
Reset and clock control (RCC) RM0008 programmed in alternate function mode. One of 4 clock signals can be selected as the MCO clock. SYSCLK PLL clock divided by 2 The selection is controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR). - Page 55 RM0008 Reset and clock control (RCC) Bit 18 HSEBYP External High Speed clock Bypass Set and reset by software in debug for bypassing oscillator with external clock. This bit can be written only if the external 1-25 MHz oscillator is disabled. 0: external 1-25 MHz oscillator not bypassed 1: external 1-25 MHz oscillator bypassed with external clock Bit 17 HSERDY External High Speed clock ready flag...
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Page 56: Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0008 4.3.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. Reserved MCO[2:0] Res. - Page 57 RM0008 Reset and clock control (RCC) Bits 21:18 PLLMUL PLL Multiplication Factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4...
- Page 58 Reset and clock control (RCC) RM0008 Bits 10:8 PPRE1 APB Low speed prescaler (APB1) Set and reset by software to control APB Low speed clocks division factor. Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain. 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4...
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Page 59: Clock Interrupt Register (Rcc_Cir)
RM0008 Reset and clock control (RCC) 4.3.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Reserved CSSC Reserved RDYC RDYC RDYC RDYC RDYC Res. Reserved CSSF Reserved RDYIE RDYIE RDYIE RDYIE... - Page 60 Reset and clock control (RCC) RM0008 Bit 16 LSIRDYC LSI Ready Interrupt Clear Set by software to clear LSIRDYF. Reset by hardware when clear done. 0: LSIRDYF not cleared 1: LSIRDYF cleared Bits 15:13 Reserved, always read as 0. Bit 12 PLLRDYIE PLL Ready Interrupt Enable Set and reset by software to enable/disable interrupt caused by PLL lock.
- Page 61 RM0008 Reset and clock control (RCC) Bit 2 HSIRDYF HSI Ready Interrupt flag Reset by software by writing HSIRDYC. Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF LSE Ready Interrupt flag Reset by software by writing LSERDYC.
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Page 62: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Reset and clock control (RCC) RM0008 4.3.4 APB2 Peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Reserved Res. USART SPI1 TIM1 ADC2 ADC1 IOPE IOPD IOPC IOPB IOPA AFIO Res. - Page 63 RM0008 Reset and clock control (RCC) Bit 5 IOPDRST IO port D reset Set and reset by software. 0: No effect 1: Reset I/O port D Bit 4 IOPCRST IO port C reset Set and reset by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST IO port B reset Set and reset by software.
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Page 64: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
Reset and clock control (RCC) RM0008 4.3.5 APB1 Peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access USART USART I2C2 I2C1 Reserved Res. Res. Reserved Res. Res. Res. Res. Res. - Page 65 RM0008 Reset and clock control (RCC) Bit 18 USART3RST USART 3 reset Set and reset by software. 0: No effect 1: Reset USART 3 Bit 17 USART2RST USART 2 reset Set and reset by software. 0: No effect 1: Reset USART 2 Bits 16:15 Reserved, always read as 0.
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Page 66: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
Reset and clock control (RCC) RM0008 4.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access Reserved FLITF SRAM Reserved Res. Res. Bits 31:5 Reserved, always read as 0. Bit 4 FLITFEN FLITF clock enable Set and reset by software to disable/enable FLITF clock during sleep mode. -
Page 67: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0008 Reset and clock control (RCC) 4.3.7 APB2 Peripheral Clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in APB2 domain is on going. - Page 68 Reset and clock control (RCC) RM0008 Bit 6 IOPEEN I/O port E clock enable Set and reset by software. 0: I/O port E clock disabled 1: I/O port E clock enabled Bit 5 IOPDEN I/O port D clock enable Set and reset by software. 0: I/O port D clock disabled 1: I/O port D clock enabled Bit 4 IOPCEN I/O port C clock enable...
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Page 69: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
RM0008 Reset and clock control (RCC) 4.3.8 APB1 Peripheral Clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. - Page 70 Reset and clock control (RCC) RM0008 Bits 20:19 Reserved, always read as 0. Bit 18 USART3EN USART 3 clock enable Set and reset by software. 0: USART 3 clock disabled 1: USART 3 clock enabled Bit 17 USART2EN USART 2 clock enable Set and reset by software.
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Page 71: Backup Domain Control Register (Rcc_Bdcr)
RM0008 Reset and clock control (RCC) 4.3.9 Backup domain control register (RCC_BDCR) Address: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register... -
Page 72: Control/Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0008 Bit 1 LSERDY External Low Speed oscillator Ready Set and reset by hardware to indicate when the external 32 kHz oscillator is stable. This bit needs 6 cycles of external Low Speed oscillator clock to fall down after LSEON reset. 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 0 LSEON External Low Speed oscillator enable... - Page 73 RM0008 Reset and clock control (RCC) Bit 28 SFTRSTF Software Reset flag Reset by software by writing the RMVF bit. Set by hardware when a software reset occurs. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF POR/PDR reset flag Reset by software by writing the RMVF bit.
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Page 74: Rcc Register Map
Reset and clock control (RCC) RM0008 RCC register map Table 10. RCC - register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 000h Reserved Reserved Reset value PPRE2 PPRE1 RCC_CFGR MCO [2:0] PLLMUL[3:0] HPRE[3:0] [2:0] [2:0] [1:0] [1:0] 004h Reserved [1:0] Reset value... -
Page 75: General-Purpose And Alternate-Function I/Os (Gpios And Afios)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO functional description Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR). -
Page 76: Figure 9. Basic Structure Of A Standard I/O Port Bit
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Figure 9. Basic structure of a standard I/O port bit Analog Input To on-chip peripheral on/off Alternate Function Input on/off Read TTL Schmitt Protection trigger on/off diode Input driver I/O pin Write Output driver Protection diode... -
Page 77: Table 12. Output Mode Bits
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 11. Port bit configuration table PxODR Configuration mode CNF1 CNF0 MODE1 MODE0 Register Push-pull 0 or 1 General purpose output Open-drain 0 or 1 Push-pull don’t care Alternate Function Table 12 output Open-drain don’t care... -
Page 78: General-Purpose I/O (Gpio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 5.1.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b). The JTAG pins are in input PU/PD after reset: PA15: JTDI in PU PA14: JTCK in PD PA13: JTMS in PU... -
Page 79: Software Remapping Of I/O Alternate Functions
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) If you configure a port bit as Alternate Function Output, this disconnects the output register and connects the pin to the output signal of an on-chip peripheral. If software configures a GPIO pin as Alternate Function Output, but peripheral is not activated, its output is not specified. -
Page 80: Output Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 5.1.8 Output configuration When the I/O Port is programmed as Output: The Output Buffer is enabled: – Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register leaves the port in Hi-Z. -
Page 81: Analog Input Configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 13 on page 81 shows the Alternate Function Configuration of the I/O Port bit. Also, refer to Section 5.4: AFIO register description on page 92 for further information. A set of Alternate Function I/O registers allow you to remap some alternate functions to different pins. -
Page 82: Figure 14. High Impedance-Analog Input Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Figure 14. High impedance-analog input configuration Analog Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Protection diode Read/write From on-chip peripheral ai14786 82/501... -
Page 83: Gpio Register Description
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 5.2.1 Port configuration register low (GPIOx_CRL) (x=A..E) Address offset: 0x00 Reset value: 0x4444 4444 CNF7[1:0] MODE7[1:0] CNF6[1:0]... -
Page 84: Port Configuration Register High (Gpiox_Crh) (X=A..e
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 5.2.2 Port configuration register high (GPIOx_CRH) (x=A..E) Address offset: 0x04 Reset value: 0x4444 4444 CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0] CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0] Bits 31:30, 27:26, 23:22, CNFy[1:0]: Port x configuration bits (y= 8 .. -
Page 85: Port Input Data Register (Gpiox_Idr) (X=A..e
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 5.2.3 Port input data register (GPIOx_IDR) (x=A..E) Address offset: 0x08h Reset value: 0x00000000 Reserved IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Bits 31:16 Reserved, always read as 0. Bits 31:0 IDRy[15:0]: Port input data (y= 0 .. -
Page 86: Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 5.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..E) Address offset: 0x10 Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 BR10 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. -
Page 87: Port Configuration Lock Register (Gpiox_Lckr) (X=A..e
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 5.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..E) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. -
Page 88: Alternate Function I/O And Debug Configuration (Afio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Alternate function I/O and debug configuration (AFIO) To optimize the number of peripherals available for the 64-pin or the 100-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the AF remap and debug I/O configuration register (AFIO_MAPR) on page... -
Page 89: Timer Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 14. Debug interface signals (continued) Alternate function GPIO port JTDI PA15 JTDO / TRACESWO JNTRST TRACECK TRACED0 TRACED1 TRACED2 TRACED3 To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register... -
Page 90: Table 17. Timer 3 Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 16. Timer 4 alternate function remapping Alternate function TIM4_REMAP = 0 TIM4_REMAP = 1 TIM4_CH3 PD14 TIM4_CH4 PD15 1. Remap available only for 100-pin package. Table 17. Timer 3 alternate function remapping TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = TIM3_REMAP[1:0] =... -
Page 91: Usart Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 5.3.6 USART Alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 20. USART3 remapping USART3_REMAP[1:0] USART3_REMAP[1:0] USART3_REMAP[1:0] Alternate function = “01” (partial remap) = “00” (no remap) = “11”... -
Page 92: Afio Register Description
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 24. SPI1 remapping Alternate function SPI1_REMAP = 0 SPI1_REMAP = 1 SPI1_NSS PA15 SPI1_SCK SPI1_MISO SPI1_MOSI AFIO register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 5.4.1 Event control register (AFIO_EVCR) Address offset: 0x00... -
Page 93: Af Remap And Debug I/O Configuration Register (Afio_Mapr)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 5.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Address offset: 0x04 Reset value: 0x0000 0000 SWJ_ Reserved Reserved CFG[2:0] USART USART PD01_ CAN_REMAP TIM4_ TIM3_REMAP TIM2_REMAP TIM1_REMAP USART3_ I2C1_ SPI1_ REMAP [1:0] REMAP [1:0]... - Page 94 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 11:10 TIM3_REMAP[1:0] TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
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Page 95: External Interrupt Configuration Register 1 (Afio_Exticr1)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 0 SPI1_REMAP SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) 5.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) -
Page 96: External Interrupt Configuration Register 3 (Afio_Exticr3)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 5.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 Reserved EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin... -
Page 97: Gpio And Afio Register Maps
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO and AFIO register maps Refer to Table 1 on page 27 for the register boundary addresses. 5.5.1 GPIO register map Table 25. GPIO register map and reset values Offset Register MODE MODE MODE MODE... -
Page 98: Interrupts And Events
Interrupts and events RM0008 Interrupts and events Nested vectored interrupt controller (NVIC) Features 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) 16 programmable priority levels (4 bits of interrupt priority are used) Low-latency exception and interrupt handling Power management control Implementation of System Control Registers The NVIC and the processor core interface are closely coupled, which enables low latency... - Page 99 RM0008 Interrupts and events Table 27. Vector table (continued) Type of Acronym Description Address priority settable SysTick System tick timer 0x0000_003C settable WWDG Window Watchdog interrupt 0x0000_0040 PVD through EXTI Line detection settable 0x0000_0044 interrupt settable TAMPER Tamper interrupt 0x0000_0048 settable RTC global interrupt 0x0000_004C...
- Page 100 Interrupts and events RM0008 Table 27. Vector table (continued) Type of Acronym Description Address priority settable TIM4 TIM4 global interrupt 0x0000_00B8 settable I2C1_EV C1 event interrupt 0x0000_00BC settable I2C1_ER C1 error interrupt 0x0000_00C0 settable I2C2_EV C2 event interrupt 0x0000_00C4 settable I2C2_ER C2 error interrupt 0x0000_00C8...
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Page 101: External Interrupt/Event Controller (Exti)
RM0008 Interrupts and events External interrupt/event controller (EXTI) The external interrupt/event controller consists of up to 19 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (pulse or pending) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. -
Page 102: Wakeup Event Management
Interrupts and events RM0008 6.2.3 Wakeup event management Cortex™-M3 is able to handle external events or internal events in order to wake up the core (WFE). By configuring the external lines any I/O port, RTC Alarm and USB Wakeup Events can be used to wake up the CPU (exit from WFE). -
Page 103: External Interrupt/Event Line Mapping
RM0008 Interrupts and events 6.2.5 External interrupt/event line mapping The 80 GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 16. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15... - Page 104 Interrupts and events RM0008 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved MR18 MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10 Bits 31:19 Reserved, must be kept at reset value (0). Bits 18:0 MRx: Interrupt Mask on line x 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Event mask register (EXTI_EMR)
- Page 105 RM0008 Interrupts and events Rising Trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 Reserved TR18 TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:19 Reserved, must be kept at reset value (0). Bits 18:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line.
- Page 106 Interrupts and events RM0008 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER Reserved SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:19 Reserved, must be kept at reset value (0). Bits 18:0 SWIERx: Software Interrupt on line x Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR.
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Page 107: Exti Register Map
RM0008 Interrupts and events 6.3.1 EXTI register map Table 28. External interrupt/event controller register map and reset values Offset Register EXTI_IMR MR[18:0] Reserved Reset value EXTI_EMR MR[18:0] Reserved Reset value EXTI_RTSR TR[18:0] Reserved Reset value EXTI_FTSR TR[18:0] Reserved Reset value EXTI_SWIER SWIER[18:0] Reserved... -
Page 108: Dma Controller (Dma)
DMA controller (DMA) RM0008 DMA controller (DMA) Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The DMA controller has 7 channels, each dedicated to managing memory access requests from one or more peripherals. -
Page 109: Functional Description
RM0008 DMA controller (DMA) Figure 17. DMA block diagram ICode Flash FLITF DCode Cortex-M3 System SRAM AHB System Bus Bridge 1 Ch.1 Bridge 2 APB2 APB1 Ch.2 USART2 Ch.7 TIM2 USART1 USART3 TIM3 SPI2 SPI1 TIM4 I2C1 Arbiter I2C2 ADC1 TIM1 AHB Slave DMA Request... -
Page 110: Arbiter
DMA controller (DMA) RM0008 7.3.2 Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: Software: each channel priority can be configured in the DMA_CCRx register. There are four levels: –... -
Page 111: Error Management
RM0008 DMA controller (DMA) Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event. -
Page 112: Dma Request Mapping
DMA controller (DMA) RM0008 7.3.5 DMA request mapping The 7 requests from the peripherals (TIMx, ADC, SPIx, I Cx and USARTx) are simply logically ORed before entering DMA, this means that only one request must be enabled at a time. Refer to Figure 18: DMA request mapping. -
Page 113: Dma Registers
RM0008 DMA controller (DMA) Table 29. Summary of DMA requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 SPI1_RX SPI1_TX SPI2_RX SPI2_TX USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I2C2_TX I2C2_RX I2C1_TX... -
Page 114: Dma Interrupt Flag Clear Register (Dma
DMA controller (DMA) RM0008 Bits 25, 21, TCIFx: Channel x Transfer Complete flag (x = 1 ..7) 17, 13, 9, 5, This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. -
Page 115: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1
RM0008 DMA controller (DMA) 7.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) Address offset: 0x08 + 20d × Channel number Reset value: 0x0000 0000 Reserved MEM2 PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC TEIE HTIE TCIE Res. Bits 31:15 Reserved, always read as 0. Bit 14 MEM2MEM: Memory to memory mode This bit is set and cleared by software. -
Page 116: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
DMA controller (DMA) RM0008 Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. -
Page 117: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1
RM0008 DMA controller (DMA) 7.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) Address offset: 0x10 + 20d × Channel number Reset value: 0x0000 0000 Bits 31:0 PA[31:0]: Peripheral Address Base address of the peripheral data register from/to which the data will be read/written. 7.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7) Address offset: 0x14 + 20d ×... - Page 118 DMA controller (DMA) RM0008 Table 30. DMA - register map and reset values (continued) Offset Register DMA_CMAR2 MA[31:0] 028h Reset value 02Ch Reserved PSIZE DMA_CCR3 SIZE [1:0] [1:0] 030h Reserved [1:0] Reset value DMA_CNDTR3 NDT[15:0] 034h Reserved Reset value DMA_CPAR3 PA[31:0] 038h Reset value...
- Page 119 RM0008 DMA controller (DMA) Table 30. DMA - register map and reset values (continued) Offset Register DMA_CNDTR6 NDT[15:0] 070h Reserved Reset value DMA_CPAR6 PA[31:0] 074h Reset value DMA_CMAR6 MA[31:0] 078h Reset value 07Ch Reserved PSIZE DMA_CCR7 SIZE [1:0] [1:0] 080h Reserved [1:0] Reset value...
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Page 120: Real-Time Clock (Rtc)
Real-time clock (RTC) RM0008 Real-time clock (RTC) Introduction The real-time clock is an independent timer. The RTC provides a set of continuously running counters which can be used, with suitable software, to provide a clock-calendar function. The counter values can be written to set the current time/date of the system. The RTC core and clock configuration (RCC_BDCR register) are in the Backup domain, which means that RTC setting and time are kept after reset or wakeup from Standby mode. -
Page 121: Figure 19. Rtc Simplified Block Diagram
RM0008 Real-time clock (RTC) time is incremented at the TR_CLK rate and compared with a programmable date (stored in the RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR control register. Figure 19. RTC simplified block diagram APB1 bus PCLK1 APB1 interface... -
Page 122: Resetting Rtc Registers
Real-time clock (RTC) RM0008 8.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset. -
Page 123: Configuring Rtc Registers
RM0008 Real-time clock (RTC) 8.3.4 Configuring RTC registers To write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter Configuration Mode. This is done by setting the CNF bit in the RTC_CRL register. In addition, writing to any RTC register is only enabled if the previous write operation is finished. -
Page 124: Rtc Register Description
Real-time clock (RTC) RM0008 Figure 21. RTC Overflow waveform example with PR=0003 RTCCLK RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second FFFFFFFC FFFFFFFD FFFFFFFE FFFFFFFF... -
Page 125: Rtc Control Register Low (Rtc_Crl)
RM0008 Real-time clock (RTC) 8.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 Reserved RTOFF ALRF SECF rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not. - Page 126 Real-time clock (RTC) RM0008 The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 8.3.4 on page 123).
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Page 127: Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll)
RM0008 Real-time clock (RTC) 8.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) The Prescaler Load registers keep the period counting value of the RTC prescaler. They are write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. -
Page 128: Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl)
Real-time clock (RTC) RM0008 8.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) During each period of TR_CLK, the counter inside the RTC prescaler is reloaded with the value stored in the RTC_PRL register. To get an accurate time measurement it is possible to read the current value of the prescaler counter, stored in the RTC_DIV register, without stopping it. -
Page 129: Rtc Counter Register (Rtc_Cnth / Rtc_Cntl)
RM0008 Real-time clock (RTC) 8.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. -
Page 130: Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl)
Real-time clock (RTC) RM0008 8.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. -
Page 131: Rtc Register Map
RM0008 Real-time clock (RTC) RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 31. - register map and reset values Offset Register RTC_CRH 000h Reserved Reset value RTC_CRL 004h Reserved Reset value RTC_PRLH PRL[19:16] 008h... -
Page 132: Backup Registers (Bkp)
Backup registers (BKP) RM0008 Backup registers (BKP) Introduction The backup registers are ten 16-bit registers for storing 20 bytes of user application data. They are implemented in the backup domain that remains powered on by V when the power is switched off. They are not reset when the device wakes up from Standby mode or by a system reset or power reset. -
Page 133: Rtc Calibration
RM0008 Backup registers (BKP) Note: Tamper detection is still active when V power is switched off. To avoid unwanted resetting of the data backup registers, the TAMPER pin should be externally tied to the correct level. RTC calibration For measurement purposes, the 32.768 kHz RTC clock can be output on the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register (BKP_RTCCR). -
Page 134: Backup Control Register (Bkp_Cr)
Backup registers (BKP) RM0008 Bit 8 ASOE Alarm or Second Output Enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one LSE period. The TAMPER pin must not be enabled while the ASOE bit is set. -
Page 135: Backup Control/Status Register (Bkp_Csr)
RM0008 Backup registers (BKP) 9.5.4 Backup control/status register (BKP_CSR) Address offset: 0x34 Reset value: 0x0000 0000 Reserved Reserved TPIE Res. Res. Bits 15:10 Reserved, always read as 0. Bit 9 TIF Tamper Interrupt Flag This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt). -
Page 136: Bkp Register Map
Backup registers (BKP) RM0008 BKP register map BKP registers are mapped as 16-bit addressable registers as described in the table below: Table 32. BKP - register map and reset values Offset Register Reserved BKP_DR1 D[15:0] Reserved Reset value BKP_DR2 D[15:0] Reserved Reset value BKP_DR3... -
Page 137: Independent Watchdog (Iwdg)
RM0008 Independent watchdog (IWDG) Independent watchdog (IWDG) The STM32F10xxx has two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both Watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (Window Watchdog only) when the counter reaches a given timeout value. -
Page 138: Table 33. Watchdog Timeout Period (With 40 Khz Input Clock)
Independent watchdog (IWDG) RM0008 Figure 22. Independent watchdog block diagram 1.8 V voltage domain Prescaler Register Status Register Reload Register Key Register IWDG_PR IWDG_SR IWDG_RLR IWDG_KR 12-bit reload value 8-bit Prescaler (40 kHz) IWDG RESET 12-bit Down-counter VDD voltage domain Note: The watchdog function is implemented in the V voltage domain that is still functional in... -
Page 139: Iwdg Register Description
RM0008 Independent watchdog (IWDG) 10.2 IWDG register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 10.2.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Reserved KEY[15:0] Bits 31:16 Reserved, read as 0. -
Page 140: Reload Register (Iwdg_Rlr)
Independent watchdog (IWDG) RM0008 Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection 10.1.2. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. -
Page 141: Status Register (Iwdg_Sr)
RM0008 Independent watchdog (IWDG) 10.2.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Reserved Reserved Bits 31:2 Reserved Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V voltage domain (takes up to 5 RC 40 kHz cycles). -
Page 142: Iwdg Register Map
Independent watchdog (IWDG) RM0008 10.3 IWDG register map Table 34. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] Reserved Reset value IWDG_PR PR[2:0] Reserved Reset value IWDG_RLR RL[11:0] Reserved Reset value IWDG_SR Reserved Reset value Refer to Table 1 on page 27 for the register boundary addresses. -
Page 143: Window Watchdog (Wwdg)
RM0008 Window watchdog (WWDG) Window watchdog (WWDG) 11.1 Introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. -
Page 144: How To Program The Watchdog Timeout
Window watchdog (WWDG) RM0008 Figure 23. Watchdog block diagram Watchdog Configuration Register (WWDG_CFR) RESET comparator = 1 when T6:0 > W6:0 Write WWDG_CR Watchdog Control Register (WWDG_CR) WDGA 6-bit downcounter (CNT) PCLK1 (from RCC clock controller) WDG prescaler (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. -
Page 145: Debug Mode
RM0008 Window watchdog (WWDG) used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 24. -
Page 146: Register Description
Window watchdog (WWDG) RM0008 11.6 Register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 11.6.1 Control Register (WWDG_CR) Address offset: 0x00 Reset value: 0x7F Reserved Res. Reserved WDGA Res. Bits 31:8 Reserved Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. -
Page 147: Status Register (Wwdg_Sr)
RM0008 Window watchdog (WWDG) Bits 8:7 WDGTB[1:0]: Timer Base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK1 div 4096) div 1 01: CK Counter Clock (PCLK1 div 4096) div 2 10: CK Counter Clock (PCLK1 div 4096) div 4 11: CK Counter Clock (PCLK1 div 4096) div 8 Bits 6:0 W[6:0] 7-bit window value These bits contain the window value to be compared to the downcounter. -
Page 148: Advanced Control Timer (Tim1)
Advanced control timer (TIM1) RM0008 Advanced control timer (TIM1) 12.1 Introduction The advanced control timer (TIM1) consists of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). -
Page 149: Block Diagram
RM0008 Advanced control timer (TIM1) 12.3 Block diagram Figure 25. Advanced control timer (TIM1) block diagram Internal Clock (CK_INT) TIM1CLK from RCC ETRF Trigger ETRP Controller Polarity Selection & Edge TRGO Input Filter TIM1_ETR Detector & Prescaler to other timers from TIM2 (ITR1) Slave from TIM3 (ITR2) -
Page 150: Functional Description
Advanced control timer (TIM1) RM0008 12.4 Functional description 12.4.1 Time base unit The main block of the programmable advanced control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. -
Page 151: Counter Modes
RM0008 Advanced control timer (TIM1) Figure 26. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIM1_PSC Prescaler buffer Prescaler counter Figure 27. -
Page 152: Figure 28. Counter Timing Diagram, Internal Clock Divided By 1
Advanced control timer (TIM1) RM0008 preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIM1_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). -
Page 153: Figure 30. Counter Timing Diagram, Internal Clock Divided By 4
RM0008 Advanced control timer (TIM1) Figure 30. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 31. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register... -
Page 154: Figure 33. Counter Timing Diagram, Update Event When Arpe=1 (Tim1_Arr Preloaded)
Advanced control timer (TIM1) RM0008 Figure 33. Counter timing diagram, update event when ARPE=1 (TIM1_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register... -
Page 155: Figure 34. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 Advanced control timer (TIM1) Figure 34. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 35. -
Page 156: Figure 37. Counter Timing Diagram, Internal Clock Divided By N
Advanced control timer (TIM1) RM0008 Figure 37. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 38. Counter timing diagram, update event when repetition counter is not used CK_PSC CNT_EN... -
Page 157: Figure 39. Counter Timing Diagram, Internal Clock Divided By 1, Tim1_Arr=0X6
RM0008 Advanced control timer (TIM1) In addition, if the URS bit (update request selection) in TIM1_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. -
Page 158: Figure 41. Counter Timing Diagram, Internal Clock Divided By 4, Tim1_Arr=0X36
Advanced control timer (TIM1) RM0008 Figure 41. Counter timing diagram, internal clock divided by 4, TIM1_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow Update event (UEV) Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 42. -
Page 159: Repetition Downcounter
RM0008 Advanced control timer (TIM1) Figure 44. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F8 F9 FA FB FC 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIM1_ARR... -
Page 160: Figure 45. Update Rate Examples Depending On Mode And Tim1_Rcr Register Settings
Advanced control timer (TIM1) RM0008 Figure 45. Update rate examples depending on mode and TIM1_RCR register settings Center-aligned mode Edge-aligned mode Upcounting Downcounting Counter TIM1_CNT TIM1_RCR = 0 TIM1_RCR = 1 TIM1_RCR = 2 TIM1_RCR = 3 TIM1_RCR re-synchronization (by SW) (by SW) (by SW) UEV Update Event: Preload registers transferred to active registers and update interrupt generated... -
Page 161: Clock Selection
RM0008 Advanced control timer (TIM1) 12.4.4 Clock selection The counter clock can be provided by the following clock sources: Internal clock (CK_INT) External clock mode1: external input pin External clock mode2: external trigger input ETR Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2. -
Page 162: Figure 48. Control Circuit In External Clock Mode 1
Advanced control timer (TIM1) RM0008 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIM1_CCMR1 register. -
Page 163: Capture/Compare Channels
RM0008 Advanced control timer (TIM1) For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIM1_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIM1_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIM1_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIM1_SMCR register. -
Page 164: Figure 51. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced control timer (TIM1) RM0008 Figure 51. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_rising TI1F TI1FP1 filter Edge downcounter Detector TI1F_falling TI2FP1 IC1PS divider /1, /2, /4, /8 ICF[3:0] CC1P (from slave mode TIM1_CCMR1 TIM1_CCER controller) -
Page 165: Input Capture Mode
RM0008 Advanced control timer (TIM1) Figure 53. Output stage of capture/compare channel (channel 1 to 3) Output enable ‘0’ circuit OC1_DT CC1P CNT>CCR1 OC1REF Output mode Dead-time TIM1_CCER CNT=CCR1 controller generator OC1N_DT OC1N Output ‘0’ enable circuit CC1NE CC1E TIM1_CCER OC1CE OC1M[2:0] DTG[7:0]... -
Page 166: Pwm Input Mode
Advanced control timer (TIM1) RM0008 The following example shows how to capture the counter value in TIM1_CCR1 when TI1 input rises. To do this, use the following procedure: Select the active input: TIM1_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIM1_CCMR1 register. -
Page 167: Forced Output Mode
RM0008 Advanced control timer (TIM1) For example, you can measure the period (in TIM1_CCR1 register) and the duty cycle (in TIM1_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): Select the active input for TIM1_CCR1: write the CC1S bits to 01 in the TIM1_CCMR1 register (TI1 selected). -
Page 168: Output Compare Mode
Advanced control timer (TIM1) RM0008 12.4.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIM1_CCMRx register) and the output polarity... -
Page 169: Pwm Mode
RM0008 Advanced control timer (TIM1) Figure 56. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A B200 B201 003B TIM1_CCR1 003A B201 oc1ref=OC1 Match detected on CCR1 Interrupt generated if enabled 12.4.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIM1_ARR register and a duty cycle determined by the value of the TIM1_CCRx register. -
Page 170: Figure 57. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced control timer (TIM1) RM0008 compare value in TIM1_CCRx is greater than the auto-reload value (in TIM1_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 57 shows some edge-aligned PWM waveforms in an example where TIM1_ARR=8. -
Page 171: Figure 58. Center-Aligned Pwm Waveforms (Arr=8)
RM0008 Advanced control timer (TIM1) Figure 58. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx = 7 CMS=10 or 11 CCxIF OCxREF CCRx = 8 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx > 8 CMS=01 CCxIF CMS=10... -
Page 172: Complementary Outputs And Dead-Time Insertion
Advanced control timer (TIM1) RM0008 12.4.11 Complementary outputs and dead-time insertion The Advanced Control Timer TIM1 can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) -
Page 173: Using The Break Function
RM0008 Advanced control timer (TIM1) Figure 61. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIM1_BDTR register. Refer to Section 12.5.18: Break and dead-time register (TIM1_BDTR) on page 209 for delay calculation. - Page 174 Advanced control timer (TIM1) RM0008 When a break occurs (selected level on the break input): The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
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Page 175: Figure 62. Output Behavior In Response To A Break
RM0008 Advanced control timer (TIM1) Figure 62. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay... -
Page 176: Clearing The Ocxref Signal On An External Event
Advanced control timer (TIM1) RM0008 12.4.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIM1_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs. -
Page 177: 6-Step Pwm Generation
RM0008 Advanced control timer (TIM1) 12.4.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. -
Page 178: One-Pulse Mode
Advanced control timer (TIM1) RM0008 12.4.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. -
Page 179: Encoder Interface Mode
RM0008 Advanced control timer (TIM1) value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIM1_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIM1_CCMR1 register and ARPE in the TIM1_CR1 register. In this case you have to write the compare value in the TIM1_CCR1 register, the auto-reload value in the TIM1_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. -
Page 180: Table 36. Counting Direction Versus Encoder Signals
Advanced control timer (TIM1) RM0008 Table 36. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite Active edge signal (TI1FP1 Rising Falling Rising Falling for TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count... -
Page 181: Timer Input Xor Function
RM0008 Advanced control timer (TIM1) Figure 67 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 67. Example of encoder interface mode with TI1FP1 polarity inverted. forward jitter backward jitter forward Counter down down... - Page 182 Advanced control timer (TIM1) RM0008 The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced control timer TIM1 (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode).
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Page 183: Figure 68. Example Of Hall Sensor Interface
RM0008 Advanced control timer (TIM1) Figure 68. Example of hall sensor interface TIH1 TIH2 TIH3 counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step 183/501... -
Page 184: Tim1 And External Trigger Synchronization
Advanced control timer (TIM1) RM0008 12.4.19 TIM1 and external trigger synchronization The TIM1 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIM1_CR1 register is low, an update event UEV is generated. -
Page 185: Figure 70. Control Circuit In Gated Mode
RM0008 Advanced control timer (TIM1) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). -
Page 186: Figure 71. Control Circuit In Trigger Mode
Advanced control timer (TIM1) RM0008 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). -
Page 187: Timer Synchronization
RM0008 Advanced control timer (TIM1) Configure the external trigger input circuit by programming the TIM1_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. -
Page 188: Tim1 Register Description
Advanced control timer (TIM1) RM0008 12.5 TIM1 register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 12.5.1 Control register 1 (TIM1_CR1) Address offset: 0x00 Reset value: 0x0000 Reserved CKD[1:0] ARPE CMS[1:0] UDIS Res. - Page 189 RM0008 Advanced control timer (TIM1) Bit 2 URS: Update request source. This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
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Page 190: Control Register 2 (Tim1_Cr2)
Advanced control timer (TIM1) RM0008 12.5.2 Control register 2 (TIM1_CR2) Address offset: 0x04 Reset value: 0x0000 Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC Res. Res. Bit 15 Reserved, always read as 0 Bit 14 OIS4: Output Idle state 4 (OC4 output). refer to OIS1 bit Bit 13 OIS3N: Output Idle state 3 (OC3N output). - Page 191 RM0008 Advanced control timer (TIM1) Bits 6:4 MMS[1:0]: Master Mode Selection. These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIM1_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
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Page 192: Slave Mode Control Register (Tim1_Smcr)
Advanced control timer (TIM1) RM0008 12.5.3 Slave mode control register (TIM1_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity. This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. - Page 193 RM0008 Advanced control timer (TIM1) Bits 11:8 ETF[3:0]: External trigger filter. This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
- Page 194 Advanced control timer (TIM1) RM0008 Bits 2:0 SMS Slave mode selection. When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1’...
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Page 195: Dma/Interrupt Enable Register (Tim1_Dier)
RM0008 Advanced control timer (TIM1) 12.5.4 DMA/Interrupt enable register (TIM1_DIER) Address offset: 0x0C Reset value: 0x0000 COMD CC4D CC3D CC2D CC1D COMI Res. CC4IE CC3IE CC2IE CC1IE Res. Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable. 0: Trigger DMA request disabled. -
Page 196: Status Register (Tim1_Sr)
Advanced control timer (TIM1) RM0008 Bit 3 CC3IE: Capture/Compare 3 interrupt enable. 0: CC3 interrupt disabled. 1: CC3 interrupt enabled. Bit 2 CC2IE: Capture/Compare 2 interrupt enable. 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable. 0: CC1 interrupt disabled. - Page 197 RM0008 Advanced control timer (TIM1) Bit 5 COMIF: COM interrupt Flag. This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending.
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Page 198: Event Generation Register (Tim1_Egr)
Advanced control timer (TIM1) RM0008 12.5.6 Event generation register (TIM1_EGR) Address offset: 0x14 Reset value: 0x0000 Reserved COMG CC4G CC3G CC2G CC1G Res. Bits 15:8 Reserved, always read as 0. Bit 7 BG: Break Generation. This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. -
Page 199: Capture/Compare Mode Register 1 (Tim1_Ccmr1)
RM0008 Advanced control timer (TIM1) 12.5.7 Capture/compare mode register 1 (TIM1_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. - Page 200 Advanced control timer (TIM1) RM0008 Bits 6:4 OC1M: Output Compare 1 Mode. These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 201 RM0008 Advanced control timer (TIM1) Input capture mode Bits 15:12 IC2F: Input Capture 2 Filter. Bits 11:10 IC2PSC[1:0]: Input Capture 2 Prescaler. Bits 9:8 CC2S: Capture/Compare 2 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
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Page 202: Capture/Compare Mode Register 2 (Tim1_Ccmr2)
Advanced control timer (TIM1) RM0008 12.5.8 Capture/compare mode register 2 (TIM1_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output Compare mode Bit 15 OC4CE: Output Compare 4 Clear Enable Bits 14:12 OC4M: Output Compare 4 Mode. -
Page 203: Capture/Compare Enable Register (Tim1_Ccer)
RM0008 Advanced control timer (TIM1) Input capture mode Bits 15:12 IC4F: Input Capture 4 Filter. Bits 11:10 IC4PSC: Input Capture 4 Prescaler. Bits 9:8 CC4S: Capture/Compare 4 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output. - Page 204 Advanced control timer (TIM1) RM0008 Bit 7 CC2NP: Capture/Compare 2 Complementary output Polarity. refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 Complementary output enable. refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable.
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Page 205: Table 37. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
RM0008 Advanced control timer (TIM1) Table 37. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not Output Disabled (not driven by driven by the timer) the timer) OCx=CCxP, OCx_EN=0... -
Page 206: Counter (Tim1_Cnt)
Advanced control timer (TIM1) RM0008 12.5.10 Counter (TIM1_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter Value. 12.5.11 Prescaler (TIM1_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler Value. The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1). -
Page 207: Repetition Counter Register (Tim1_Rcr)
RM0008 Advanced control timer (TIM1) 12.5.13 Repetition counter register (TIM1_RCR) Address offset: 0x30 Reset value: 0x0000 Reserved REP[7:0] Res. Bits 15:8 Reserved, always read as 0. Bits 7:0 REP[7:0]: Repetition Counter Value. These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. -
Page 208: Capture/Compare Register 2 (Tim1_Ccr2)
Advanced control timer (TIM1) RM0008 12.5.15 Capture/compare register 2 (TIM1_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 Value. If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIM1_CCMR2 register (bit OC2PE). -
Page 209: Capture/Compare Register 4 (Tim1_Ccr4)
RM0008 Advanced control timer (TIM1) 12.5.17 Capture/compare register 4 (TIM1_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare Value. If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIM1_CCMR4 register (bit OC4PE). - Page 210 Advanced control timer (TIM1) RM0008 Bit 13 BKP: Break Polarity. 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIM1_BDTR register).
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Page 211: Dma Control Register (Tim1_Dcr)
RM0008 Advanced control timer (TIM1) Bits 7:0 DTG[7:0]: Dead-Time Generator set-up. This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>... -
Page 212: Dma Address For Burst Mode (Tim1_Dmar)
Advanced control timer (TIM1) RM0008 12.5.20 DMA address for burst mode (TIM1_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses. A read or write access to the DMAR register accesses the register located at the address: “(TIM1_CR1 address) + DBA + (DMA index)”... - Page 213 RM0008 Advanced control timer (TIM1) Table 38. TIM1 - Register map and reset values (continued) Offset Register TIM1_CCMR2 OC4M CC4S OC3M CC3S Output Compare [2:0] [1:0] [2:0] [1:0] Reserved mode Reset value TIM1_CCMR2 CC4S CC3S IC4F[3:0] IC3F[3:0] Input Capture [1:0] [1:0] Reserved [1:0]...
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Page 214: General Purpose Timer (Timx)
General purpose timer (TIMx) RM0008 General purpose timer (TIMx) 13.1 Introduction The General purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). -
Page 215: Block Diagram
RM0008 General purpose timer (TIMx) 13.3 Block diagram Figure 73. General-purpose timer block diagram Internal Clock (CK_INT) TIMXCLK from RCC ETRF ETRP Polarity Selection & Edge Input Filter TIMx_ETR Detector & Prescaler TRGO TIM1 (ITR0) Trigger to other timers Controller TIM2 (ITR1) TIM3 (ITR2) TRGI... -
Page 216: Figure 74. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General purpose timer (TIMx) RM0008 The Time Base Unit includes: Counter Register (TIMx_CNT) Prescaler Register (TIMx_PSC): Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing or reading the auto-reload register access the preload register. The content of the preload register is transferred in the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. -
Page 217: Counter Modes
RM0008 General purpose timer (TIMx) Figure 75. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter 13.4.2... -
Page 218: Figure 76. Counter Timing Diagram, Internal Clock Divided By 1
General purpose timer (TIMx) RM0008 Figure 76. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 77. -
Page 219: Figure 79. Counter Timing Diagram, Internal Clock Divided By N
RM0008 General purpose timer (TIMx) Figure 79. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 80. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN... -
Page 220: Figure 81. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General purpose timer (TIMx) RM0008 Figure 81. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register... -
Page 221: Figure 82. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 General purpose timer (TIMx) Figure 82. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 83. -
Page 222: Figure 85. Counter Timing Diagram, Internal Clock Divided By N
General purpose timer (TIMx) RM0008 Figure 85. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 86. Counter timing diagram, Update event when repetition counter is not used CK_INT CNT_EN... -
Page 223: Figure 87. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0008 General purpose timer (TIMx) In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. -
Page 224: Figure 89. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36
General purpose timer (TIMx) RM0008 Figure 89. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0035 Counter overflow (cnt_ovf) Update event (UEV) Update interrupt flag (UIF) Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow Figure 90. -
Page 225: Clock Selection
RM0008 General purpose timer (TIMx) Figure 92. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register F8 F9 FA FB FC 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR... -
Page 226: Figure 93. Control Circuit In Normal Mode, Internal Clock Divided By 1
General purpose timer (TIMx) RM0008 Figure 93. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC COUNTER REGISTER 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. -
Page 227: Figure 95. Control Circuit In External Clock Mode 1
RM0008 General purpose timer (TIMx) The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 95. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 External clock source mode 2... -
Page 228: Capture/Compare Channels
General purpose timer (TIMx) RM0008 Figure 97. Control circuit in external clock mode 2 MASTER CNT_EN ETRP ETRF Counter clock = CK_CNT = CK_PSC Counter register 13.4.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). -
Page 229: Figure 99. Capture/Compare Channel 1 Main Circuit
RM0008 General purpose timer (TIMx) Figure 99. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/Compare Preload Register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/Compare Shadow Register CC1S[0] TIMx_CCMR1... -
Page 230: Input Capture Mode
General purpose timer (TIMx) RM0008 13.4.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. -
Page 231: Pwm Input Mode
RM0008 General purpose timer (TIMx) 13.4.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: Two ICx signals are mapped on the same TIx input. These 2 ICx signals are active on edges with opposite polarity. One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. -
Page 232: Output Compare Mode
General purpose timer (TIMx) RM0008 e.g.: CCxP=0 (OCx active high) => OCx is forced to high level. ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. -
Page 233: Pwm Mode
RM0008 General purpose timer (TIMx) Figure 102. Output compare mode, toggle on OC1. Write B201h in the CC1R register B200 B201 TIMx_CNT 0039 003A 003B TIMx_CCR1 003A B201 OC1REF=OC1 Match detected on CCR1 Interrupt generated if enabled 13.4.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. -
Page 234: Figure 103. Edge-Aligned Pwm Waveforms (Arr=8)
General purpose timer (TIMx) RM0008 PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Section : upcounting mode on page 217. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. -
Page 235: Figure 104. Center-Aligned Pwm Waveforms (Arr=8)
RM0008 General purpose timer (TIMx) Figure 104. Center-aligned PWM waveforms (ARR=8) Counter register OCxREF CCRx = 4 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx = 7 CMS=10 or 11 CCxIF OCxREF CCRx = 8 CMS=01 CCxIF CMS=10 CMS=11 OCxREF CCRx > 8 CMS=01 CCxIF CMS=10... -
Page 236: One Pulse Mode
General purpose timer (TIMx) RM0008 13.4.10 One pulse mode One Pulse Mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. - Page 237 RM0008 General purpose timer (TIMx) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). The t is defined by the value written in the TIMx_CCR1 register. DELAY The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
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Page 238: Clearing The Ocxref Signal On An External Event
General purpose timer (TIMx) RM0008 Particular case: OCx fast enable: In One Pulse Mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. -
Page 239: Encoder Interface Mode
RM0008 General purpose timer (TIMx) 13.4.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. -
Page 240: Figure 107. Example Of Counter Operation In Encoder Interface Mode
General purpose timer (TIMx) RM0008 selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: CC1S=’01’ (TIMx_CCMR1 register, IC1FP1 mapped on TI1). CC2S=’01’ (TIMx_CCMR2 register, IC2FP2 mapped on TI2). CC1P=’0’... -
Page 241: Timer Input Xor Function
RM0008 General purpose timer (TIMx) at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock. -
Page 242: Timers And External Trigger Synchronization
General purpose timer (TIMx) RM0008 13.4.14 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. -
Page 243: Figure 110. Control Circuit In Gated Mode
RM0008 General purpose timer (TIMx) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). -
Page 244: Figure 111. Control Circuit In Trigger Mode
General purpose timer (TIMx) RM0008 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). -
Page 245: Timer Synchronization
RM0008 General purpose timer (TIMx) Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. -
Page 246: Figure 113. Master/Slave Timer Example
General purpose timer (TIMx) RM0008 Using one timer as prescaler for the another Figure 113. Master/Slave timer example TIMER 1 TIMER 2 Clock Master Slave CK_PSC TRGO1 ITR1 mode mode control Counter Prescaler Counter Prescaler control Input trigger selection For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 113. -
Page 247: Figure 114. Gating Timer 2 With Oc1Ref Of Timer 1
RM0008 General purpose timer (TIMx) Figure 114. Gating timer 2 with OC1REF of timer 1 CK_INT TIMER1-OC1REF TIMER1-CNT TIMER2-CNT 3045 3046 3047 3048 TIMER 2-TIF Write TIF=0 In the example in Figure 114, the Timer 2 counter and prescaler are not initialized before being started. -
Page 248: Figure 115. Gating Timer 2 With Enable Of Timer 1
General purpose timer (TIMx) RM0008 Figure 115. Gating timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 113 for connections. -
Page 249: Figure 117. Triggering Timer 2 With Enable Of Timer 1
RM0008 General purpose timer (TIMx) As in the previous example, you can initialize both counters before starting counting. Figure 117 shows the behavior with the same configuration as in Figure 116 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 117. -
Page 250: Debug Mode
General purpose timer (TIMx) RM0008 counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register). -
Page 251: Timx Register Description
RM0008 General purpose timer (TIMx) 13.5 TIMx register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 13.5.1 Control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE UDIS Reserved Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD: Clock Division. - Page 252 General purpose timer (TIMx) RM0008 Bit 2 URS: Update Request Source. This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
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Page 253: Control Register 2 (Timx_Cr2)
RM0008 General purpose timer (TIMx) 13.5.2 Control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 TI1S MMS[2:0] CCDS Reserved Reserved Bits 15:8 Reserved, always read as 0. Bit 7 TI1S: TI1 Selection. 0: The TIMx_CH1 pin is connected to TI1 input. 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 12.4.18: Interfacing with Hall sensors on page 181... -
Page 254: Slave Mode Control Register (Timx_Smcr)
General purpose timer (TIMx) RM0008 13.5.3 Slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] SMS[2:0] Res. Bit 15 ETP: External Trigger Polarity. This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. - Page 255 RM0008 General purpose timer (TIMx) Bits 11:8 ETF[3:0]: External Trigger Filter. This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
- Page 256 General purpose timer (TIMx) RM0008 Bits 2:0 SMS: Slave Mode Selection. When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1’...
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Page 257: Dma/Interrupt Enable Register (Timx_Dier)
RM0008 General purpose timer (TIMx) 13.5.4 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4IE CC3IE CC2IE CC1IE Res. Res. res. res. Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable. 0: Trigger DMA request disabled. -
Page 258: Status Register (Timx_Sr)
General purpose timer (TIMx) RM0008 Bit 1 CC1IE: Capture/Compare 1 interrupt enable. 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable. 0: Update interrupt disabled. 1: Update interrupt enabled. 13.5.5 Status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Res. - Page 259 RM0008 General purpose timer (TIMx) Bit 1 CC1IF: Capture/compare 1 interrupt Flag. If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software.
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Page 260: Event Generation Register (Timx_Egr)
General purpose timer (TIMx) RM0008 13.5.6 Event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. CC4G CC3G CC2G CC1G Reserved Res. Bits 15:7 Reserved, always read as 0. Bit 6 TG: Trigger generation. This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. -
Page 261: Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0008 General purpose timer (TIMx) 13.5.7 Capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. - Page 262 General purpose timer (TIMx) RM0008 Bits 6:4 OC1M: Output Compare 1 Mode. These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
- Page 263 RM0008 General purpose timer (TIMx) Bits 9:8 CC2S: Capture/Compare 2 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
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Page 264: Capture/Compare Mode Register 2 (Timx_Ccmr2)
General purpose timer (TIMx) RM0008 13.5.8 Capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output Compare mode Bit 15 OC4CE: Output Compare 4 Clear Enable Bits 14:12 OC4M: Output Compare 4 Mode. - Page 265 RM0008 General purpose timer (TIMx) Input capture mode Bits 15:12 IC4F: Input Capture 4 Filter. Bits 11:10 IC4PSC: Input Capture 4 Prescaler. Bits 9:8 CC4S: Capture/Compare 4 Selection. This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output.
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Page 266: Capture/Compare Enable Register (Timx_Ccer)
General purpose timer (TIMx) RM0008 13.5.9 Capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC4P CC4E CC3P CC3E CC2P CC2E CC1P CC1E Reserved Reserved Reserved Reserved Bits 15:14 Reserved, always read as 0. Bit 13 CC4P: Capture/Compare 4 output Polarity. refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable. -
Page 267: Counter (Timx_Cnt)
RM0008 General purpose timer (TIMx) Table 40. Output control bit for standard OCx channels CCxE bit OCx output state Output Disabled (OCx=0, OCx_EN=0) OCx=OCxREF + Polarity, OCx_EN=1 Note: The state of the external I/O pins connected to the standard OCx channels depends on the OCx channel state and the GPIO and AFIO registers. -
Page 268: Capture/Compare Register 1 (Timx_Ccr1)
General purpose timer (TIMx) RM0008 13.5.13 Capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 Value). If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). -
Page 269: Capture/Compare Register 3 (Timx_Ccr3)
RM0008 General purpose timer (TIMx) 13.5.15 Capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 CCR3[15:0] Bits 15:0 CCR3[15:0]: Capture/Compare Value. If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). -
Page 270: Dma Control Register (Timx_Dcr)
General purpose timer (TIMx) RM0008 13.5.17 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 DBL[4:0] DBA[4:0] Reserved Reserved Bits 15:13 Reserved, always read as 0 Bits 12:8 DBL[4:0]: DMA Burst Length. This 5-bits vector defines the length of DMA transfers in burst mode (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. -
Page 271: Timx Register Map
RM0008 General purpose timer (TIMx) 13.6 TIMx register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 41. TIMx - register map and reset values Offset Register TIMx_CR1 Reserved [1:0] [1:0] Reset value TIMx_CR2 MMS[2:0] Reserved... - Page 272 General purpose timer (TIMx) RM0008 Table 41. TIMx - register map and reset values (continued) Offset Register TIMx_CCR2 CCR2[15:0] Reserved Reset value TIMx_CCR3 CCR3[15:0] Reserved Reset value TIMx_CCR4 CCR4[15:0] Reserved Reset value Reserved TIMx_DCR DBL[4:0] DBA[4:0] Reserved Reserved Reset value TIMx_DMAR DMAB[15:0] Reserved...
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Page 273: Controller Area Network (Bxcan)
RM0008 Controller area network (bxCAN) Controller area network (bxCAN) 14.1 Introduction The Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It supports the CAN protocols version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. It also meets the priority requirements for transmit messages. -
Page 274: General Description
Controller area network (bxCAN) RM0008 14.3 General description In today’s CAN applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. Typically the number of messages in the system (and thus to be handled by each node) has significantly increased. In addition to the application messages, Network Management and Diagnostic messages have been introduced. -
Page 275: Acceptance Filters
RM0008 Controller area network (bxCAN) 14.3.4 Acceptance filters The bxCAN provides 14 scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others. 14.3.5 Receive FIFO Two receive FIFOs are used by hardware to store the incoming messages. Three complete messages can be stored in each FIFO. -
Page 276: Operating Modes
Controller area network (bxCAN) RM0008 Note: ACK = The wait state during which hardware confirms a request by setting the INAK or SLAK bits in the CAN_MSR register SYNC = The state during which bxCAN waits until the CAN bus is idle, meaning 11 consecutive recessive bits have been monitored on CANRX 14.4 Operating modes... -
Page 277: Sleep Mode (Low Power)
RM0008 Controller area network (bxCAN) The initialization of the filter values is independent from Initialization Mode but must be done while the filter is not active (corresponding FACTx bit cleared). The filter scale and mode configuration must be configured before entering Normal Mode. 14.4.3 Sleep mode (low power) To reduce power consumption, bxCAN has a low-power mode called Sleep mode. -
Page 278: Loop Back Mode
Controller area network (bxCAN) RM0008 Figure 122. bxCAN in silent mode bxCAN CANTX CANRX 14.4.6 Loop back mode The bxCAN can be set in Loop Back Mode by setting the LBKM bit in the CAN_BTR register. In Loop Back Mode, the bxCAN treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) in a Receive mailbox. -
Page 279: Functional Description
RM0008 Controller area network (bxCAN) Figure 124. bxCAN in combined mode bxCAN CANTX CANRX 14.5 Functional description 14.5.1 Transmission handling In order to transmit a message, the application must select one empty transmit mailbox, set up the identifier, the data length code (DLC) and the data before requesting the transmission by setting the corresponding TXRQ bit in the CAN_TIxR register. -
Page 280: Time Triggered Communication Mode
Controller area network (bxCAN) RM0008 transmission is aborted and becomes empty with TXOK cleared. In all cases the mailbox will become empty again at least at the end of the current transmission. Non-automatic retransmission mode This mode has been implemented in order to fulfil the requirement of the Time Triggered Communication option of the CAN standard. -
Page 281: Figure 126. Receive Fifo States
RM0008 Controller area network (bxCAN) managed completely by hardware. The application accesses the messages stored in the FIFO through the FIFO output mailbox. Valid message A received message is considered as valid when it has been received correctly according to the CAN protocol (no error until the last but one bit of the EOF field) and It passed through the identifier filtering successfully, see Section 14.5.4: Identifier... -
Page 282: Identifier Filtering
Controller area network (bxCAN) RM0008 mailbox is free to store the next valid message. Otherwise the next valid message received will cause a loss of message. Refer also to Section 14.5.5: Message storage Overrun Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid message reception will lead to an overrun and a message will be lost. - Page 283 RM0008 Controller area network (bxCAN) Mask mode In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. Identifier list mode In identifier list mode, the mask registers are used as identifier registers. Thus instead of defining an identifier and a mask, two identifiers are specified, doubling the number of single identifiers.
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Page 284: Figure 127. Filter Bank Scale Configuration - Register Organization
Controller area network (bxCAN) RM0008 Figure 127. Filter bank scale configuration - register organization Filter Num. One 32-Bit Filter - Identifier Mask CAN_FxR0[31:24] CAN_FxR0[23:16] CAN_FxR0[15:8] CAN_FxR0[7:0] Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] Two 32-Bit Filters - Identifier List CAN_FxR0[31:24] CAN_FxR0[23:16] CAN_FxR0[15:8]... -
Page 285: Figure 128. Example Of Filter Numbering
RM0008 Controller area network (bxCAN) Figure 128. Example of filter numbering Filter Filter Filter Filter FIFO0 FIFO1 Bank Num. Bank Num. ID List (32-bit) ID Mask (16-bit) ID Mask (32-bit) ID List (32-bit) Deactivated ID List (16-bit) ID Mask (16-bit) Deactivated ID Mask (16-bit) ID List (32-bit) -
Page 286: Message Storage
Controller area network (bxCAN) RM0008 Figure 129. Filtering mechanism - example Example of 3 filter banks in 32-bit Unidentified List mode and the remaining in 32-bit Identifier Mask mode Message Received Identifier Data Ctrl Filter bank Receive FIFO Identifier Identifier Message Stored Identifier... -
Page 287: Table 42. Transmit Mailbox Mapping
RM0008 Controller area network (bxCAN) Table 42. Transmit mailbox mapping Offset to transmit mailbox base Register name address CAN_TIxR CAN_TDTxR CAN_TDLxR CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox. -
Page 288: Error Management
Controller area network (bxCAN) RM0008 14.5.6 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition. -
Page 289: Figure 131. Bit Timing
RM0008 Controller area network (bxCAN) A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed. -
Page 290: Interrupts
Controller area network (bxCAN) RM0008 Figure 132. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) or Overload Frame 44 + 8 * N Ctrl Field Data Field CRC Field Ack Field Arbitration Field 8 * N Inter-Frame Space Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame... -
Page 291: Figure 133. Event Flags And Interrupt Generation
RM0008 Controller area network (bxCAN) Figure 133. Event flags and interrupt generation CAN_IER TRANSMIT INTERRUPT TMEIE RQCP0 & CAN_TSR RQCP1 RQCP2 FMPIE0 & FIFO 0 FMP0 INTERRUPT FFIE0 & CAN_RF0R FULL0 FOVIE0 & FOVR0 FMPIE1 & FIFO 1 FMP1 INTERRUPT FFIE1 &... -
Page 292: Register Access Protection
Controller area network (bxCAN) RM0008 The error and status change interrupt can be generated by the following events: – Error condition, for more details on error conditions please refer to the CAN Error Status register (CAN_ESR). – Wakeup condition, SOF monitored on the CAN Rx signal. –... - Page 293 RM0008 Controller area network (bxCAN) Bits 31:16 Reserved, forced by hardware to 0. Bit 15 RESET: bxCAN software master reset 0: Normal operation. 1: Force a master reset of the bxCAN -> Sleep mode activated after reset (FMP bits and CAN_MCR register are initialized to the reset values).
- Page 294 Controller area network (bxCAN) RM0008 Bit 0 INRQ: Initialization Request The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception.
- Page 295 RM0008 Controller area network (bxCAN) Bit 1 SLAK: Sleep Acknowledge This bit is set by hardware and indicates to the software that the CAN hardware is now in Sleep mode. This bit acknowledges the Sleep mode request from the software (set SLEEP bit in CAN_MCR register).
- Page 296 Controller area network (bxCAN) RM0008 Bits 25:24 CODE[1:0]: Mailbox Code In case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free. In case all transmit mailboxes are pending, the code value is equal to the number of the transmit mailbox with the lowest priority.
- Page 297 RM0008 Controller area network (bxCAN) Bit 7 ABRQ0: Abort Request for Mailbox0 Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bits 6:4 Reserved, forced by hardware to 0.
- Page 298 Controller area network (bxCAN) RM0008 Bit 2 Reserved, forced by hardware to 0. Bits 1:0 FMP0[1:0]: FIFO 0 Message Pending These bits indicate how many messages are pending in the receive FIFO. FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased each time the software releases the output mailbox by setting the RFOM0 bit.
- Page 299 RM0008 Controller area network (bxCAN) CAN interrupt enable register (CAN_IER) Address offset: 0x14 Reset value: 0x00 Reserved SLKIE WKUIE ERRIE Reserved Res. Bits 31:18 Reserved, forced by hardware to 0. Bit 17 SLKIE: Sleep Interrupt Enable 0: No interrupt when SLAKI bit is set. 1: Interrupt generated when SLAKI bit is set.
- Page 300 Controller area network (bxCAN) RM0008 Bit 4 FMPIE1: FIFO Message Pending Interrupt Enable 0: No interrupt generated when state of FMP[1:0] bits are not 00b. 1: Interrupt generated when state of FMP[1:0] bits are not 00b. Bit 3 FOVIE0: FIFO Overrun Interrupt Enable 0: No interrupt when FOVR bit is set.
- Page 301 RM0008 Controller area network (bxCAN) CAN error status register (CAN_ESR) Address offset: 0x18 Reset value: 0x00 REC[7:0] TEC[7:0] Reserved LEC[2:0] Res. BOFF EPVF EWGF Bits 31:24 REC[7:0]: Receive Error Counter The implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard.
- Page 302 Controller area network (bxCAN) RM0008 CAN bit timing register (CAN_BTR) Address offset: 0x1C Reset value: 0x0123 0000 Note: This register can only be accessed by the software when the CAN hardware is in initialization mode. SILM LBKM Reserved SJW[1:0] Res. TS2[2:0] TS1[3:0] Reserved...
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Page 303: Mailbox Registers
RM0008 Controller area network (bxCAN) 14.8.2 Mailbox registers This chapter describes the registers of the transmit and receive mailboxes. Refer to Section 14.5.5: Message storage on page 286 for detailed register mapping. Transmit and receive mailboxes have the same registers except: The FMI field in the CAN_RDTxR register. - Page 304 Controller area network (bxCAN) RM0008 Bit 1 RTR: Remote Transmission Request 0: Data frame 1: Remote frame Bit 0 TXRQ: Transmit Mailbox Request Set by software to request the transmission for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state.
- Page 305 RM0008 Controller area network (bxCAN) Mailbox data low register (CAN_TDLxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1A8 Reset value: 0xXX where X is undefined DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]...
- Page 306 Controller area network (bxCAN) RM0008 Rx FIFO mailbox identifier register (CAN_RIxR) (x=0..1) Address offsets: 0x1B0, 0x1C0 Reset value: 0xXX where X is undefined Note: All RX registers are write protected. STID[10:0] EXID[17:13] EXID[12:0] Res. Bits 31:21 STID[10:0]: Standard Identifier The standard part of the identifier. Bits 20:3 EXID[17:0]: Extended Identifier The extended part of the identifier.
- Page 307 RM0008 Controller area network (bxCAN) Receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1) Address offsets: 0x1B4, 0x1C4 Reset value: 0xXX where X is undefined Note: All RX registers are write protected. TIME[15:0] FMI[7:0] Reserved DLC[3:0] Bits 31:16 TIME[15:0]: Message Time Stamp This field contains the 16-bit timer value captured at the SOF detection.
- Page 308 Controller area network (bxCAN) RM0008 Bits 15:8 DATA1[7:0]: Data Byte 1 Data byte 1 of the message. Bits 7:0 DATA0[7:0]: Data Byte 0 Data byte 0 of the message. A message can contain from 0 to 8 data bytes and starts with byte 0. Receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1) Address offsets: 0x1BC, 0x1CC Reset value: 0xXX where X is undefined...
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Page 309: Can Filter Registers
RM0008 Controller area network (bxCAN) 14.8.3 CAN filter registers (these registers are implemented only in the master CAN - CAN0) CAN filter master register (CAN_FMR) Address offset: 0x200 Reset value: 0x2A1C 0E01 Note: All bits of this register are set and cleared by software. Reserved Reserved FINIT... - Page 310 Controller area network (bxCAN) RM0008 CAN filter mode register (CAN_FM0R) Address offset: 0x204 Reset value: 0x00 Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. Reserved Reserved FBM13 FBM12 FBM11 FBM10 FBM9 FBM8 FBM7...
- Page 311 RM0008 Controller area network (bxCAN) CAN filter FIFO assignment register (CAN_FFA0R) Address offset: 0x214 Reset value: 0x00 Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. Reserved Reserved FFA13 FFA12 FFA11 FFA10 FFA9...
- Page 312 Controller area network (bxCAN) RM0008 Filter bank x registers (CAN_FxR[1:0]) (x=0..13) Address offsets: 0x240..0x2AC Reset value: 0xXX where X is undefined Note: There are 14 filter banks, x=0..13. Each filter bank x is composed of two 32-bit registers, CAN_FxR[1:0]. This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared or when the FINIT bit of the CAN_FMR register is set.
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Page 313: Bxcan Register Map
RM0008 Controller area network (bxCAN) 14.9 bxCAN register map Refer to Table 1 on page 27 for the register boundary addresses. Table 44. bxCAN - register map and reset values Offset Register CAN_MCR 000h Reserved Reset value CAN_MSR 004h Reserved Reserved Reset value CAN_TSR... - Page 314 Controller area network (bxCAN) RM0008 Table 44. bxCAN - register map and reset values (continued) Offset Register CAN_TDT1R TIME[15:0] DLC[3:0] 194h Reserved Reserved Reset value CAN_TDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 198h Reset value CAN_TDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 19Ch Reset value CAN_TI2R STID[10:0] EXID[17:0]...
- Page 315 RM0008 Controller area network (bxCAN) Table 44. bxCAN - register map and reset values (continued) Offset Register CAN_FMR 200h Reserved Reset value CAN_FM0R FBM[13:0] 204h Reserved Reset value 208h Reserved CAN_FS0R FSC[13:0] 20Ch Reserved Reset value 210h Reserved CAN_FFA0R FFA[13:0] 214h Reserved Reset value...
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Page 316: Inter-Integrated Circuit (I2C) Interface
Inter-integrated circuit (I2C) interface RM0008 Inter-integrated circuit (I C) interface 15.1 Introduction C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I C bus. It provides multimaster capability, and controls all I C bus-specific sequencing, protocol, arbitration and timing. -
Page 317: General Description
RM0008 Inter-integrated circuit (I2C) interface Configurable PEC (Packet Error Checking) Generation or Verification: – PEC value can be transmitted as last byte in Tx mode – PEC error checking for last received byte SMBus 2.0 Compatibility: – 25 ms clock low timeout delay –... -
Page 318: Figure 134. I2C Bus Protocol
Inter-integrated circuit (I2C) interface RM0008 Figure 134. I C bus protocol Stop Start condition condition Acknowledge may be enabled or disabled by software. The I C interface addresses (dual addressing 7-bit/ 10-bit and/or general call address) can be selected by software. The block diagram of the I C interface is shown in Figure... -
Page 319: Figure 135. I2C Block Diagram
RM0008 Inter-integrated circuit (I2C) interface Figure 135. I C block diagram DATA REGISTER DATA DATA SHIFT REGISTER CONTROL PEC CALCULATION COMPARATOR OWN ADDRESS REGISTER DUAL ADDRESS REGISTER CLOCK PEC REGISTER CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTERS (CR1&CR2) CONTROL STATUS REGISTERS LOGIC (SR1&SR2) SMBALERT... -
Page 320: Functional Description
Inter-integrated circuit (I2C) interface RM0008 15.4 Functional description By default the I C interface operates in Slave mode. To switch from default Slave mode to Master mode a Start condition generation is needed. 15.4.1 C slave mode The peripheral input clock must be programmed in the I2C_CR2 register in order to generate correct timings. -
Page 321: Figure 136. Transfer Sequence Diagram For Slave Transmitter
RM0008 Inter-integrated circuit (I2C) interface Slave transmitter Following the address reception and after clearing ADDR, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent (see Figure 136 Transfer sequencing EV1 EV3). -
Page 322: Figure 137. Transfer Sequence Diagram For Slave Receiver
Inter-integrated circuit (I2C) interface RM0008 Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and ITBUFEN bit is set. -
Page 323: I2C Master Mode
RM0008 Inter-integrated circuit (I2C) interface 15.4.2 C master mode In Master mode, the I C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a Start condition and ends with a Stop condition. Master mode is selected as soon as the Start condition is generated on the bus with a START bit. - Page 324 Inter-integrated circuit (I2C) interface RM0008 Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. In 10-bit addressing mode, sending the header sequence causes the following event: – The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
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Page 325: Figure 138. Transfer Sequence Diagram For Master Transmitter
RM0008 Inter-integrated circuit (I2C) interface Closing the communication After writing the last byte to the DR register, the STOP bit is set by software to generate a Stop condition (see Figure 138 Transfer sequencing EV8_2). The interface goes automatically back to slave mode (M/SL bit cleared). Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set. -
Page 326: Figure 139. Transfer Sequence Diagram For Master Receiver
Inter-integrated circuit (I2C) interface RM0008 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are... -
Page 327: Error Conditions
RM0008 Inter-integrated circuit (I2C) interface 15.4.3 Error conditions The following are the error conditions which may cause communication to fail. Bus error (BERR) This error occurs when the I C interface detects a Stop or a Start condition during a byte transfer. -
Page 328: Sda/Scl Line Control
Inter-integrated circuit (I2C) interface RM0008 15.4.4 SDA/SCL line control If clock stretching is enabled: – Transmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low before transmission to wait for the microcontroller to read SR1 and then write the byte in the Data Register (both buffer and shift register are empty). -
Page 329: Table 45. Smbus Vs. I2C
RM0008 Inter-integrated circuit (I2C) interface Differences between SMBus and I The following table describes the differences between SMBus and I Table 45. SMBus vs. I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low timeout No timeout Logic levels are fixed... - Page 330 Inter-integrated circuit (I2C) interface RM0008 Unique device identifier (UDID) In order to provide a mechanism to isolate each device for the purpose of address assignment, each device must implement a unique device identifier (UDID). For the details on 128 bit UDID and more information on ARP, refer to SMBus specification ver.
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Page 331: Dma Requests
RM0008 Inter-integrated circuit (I2C) interface The application has to control the various SMBus protocols by software. SMB Device Default Address acknowledged if ENARP=1 and SMBTYPE=0 SMB Host Header acknowledged if ENARP=1 and SMBTYPE=1 SMB Alert Response Address acknowledged if SMBALERT=1 15.4.6 DMA requests DMA requests (when enabled) are generated only for data transfer. -
Page 332: Packet Error Checking
Inter-integrated circuit (I2C) interface RM0008 Reception using DMA DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register. The DMAEN bit must be set only after receiving the address sequence, when ADDR is cleared. Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received. -
Page 333: Interrupt Requests
RM0008 Inter-integrated circuit (I2C) interface 15.5 Interrupt requests Table 46. C Interrupt requests Enable Interrupt event Event flag Control bit Start bit sent (Master) Address sent (Master) or Address matched (Slave) ADDR 10-bit header sent (Master) ADD10 ITEVFEN Stop received (Slave) STOPF Data Byte Transfer Finished Receive buffer not empty... -
Page 334: I 2 C Debug Mode
Inter-integrated circuit (I2C) interface RM0008 Figure 140. I C interrupt mapping diagram ITEVFEN ADDR ADD10 STOPF it_event ITBUFEN RxNE ITERREN BERR ARLO it_error PECERR TIMEOUT SMBAlert 15.6 C debug mode When the microcontroller enters the debug mode (Cortex-M3 core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. - Page 335 RM0008 Inter-integrated circuit (I2C) interface Bit 15 SWRST: Software Reset When set, the I2C is under reset state. Before resetting this bit, make sure the I2C lines are released and the bus is free. 0: I C Peripheral not under reset 1: I C Peripheral under reset state Note:...
- Page 336 Inter-integrated circuit (I2C) interface RM0008 Bit 8 START: Start Generation This bit is set and cleared by software and cleared by hardware when start is sent or PE=0. In Master Mode: 0: No Start generation 1: Repeated start generation In Slave mode: 0: No Start generation 1: Start generation when the bus is free Bit 7 NOSTRETCH: Clock Stretching Disable (Slave mode)
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Page 337: Control Register 2 (I2C_Cr2)
RM0008 Inter-integrated circuit (I2C) interface 15.7.2 Control register 2 (I2C_CR2) Address offset: 0x04 Reset value: 0x0000 ITBUF ITEVT ITER Reserved LAST Reserved FREQ[5:0] Bits 15:13 Reserved, forced by hardware to 0. Bit 12 LAST: DMA Last Transfer 0: Next DMA EOT is not the last transfer 1: Next DMA EOT is the last transfer Note: This bit is used in master receiver mode to permit the generation of a NACK on the last received data. -
Page 338: Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I2C) interface RM0008 Bits 5:0 FREQ[5:0]: Peripheral Clock Frequency Input clock frequency must be programmed to generate correct timings The allowed range is between 2 MHz and 50 MHz 000000: Not allowed 000001: Not allowed 000010: 2 MHz 110010: 50 MHz Higher than 110010: Not allowed 15.7.3... -
Page 339: Data Register (I2C_Dr)
RM0008 Inter-integrated circuit (I2C) interface Bit 0 ENDUAL: Dual addressing mode enable 0: Only OAR1 is recognized in 7-bit addressing mode 1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode 15.7.5 Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 Reserved DR[7:0] Bits 15:8 Reserved, forced by hardware to 0. -
Page 340: Status Register 1 (I2C_Sr1)
Inter-integrated circuit (I2C) interface RM0008 15.7.6 Status register 1 (I2C_SR1) Address offset: 0x14 Reset value: 0x0000 TIME STOP Res. ARLO BERR RxNE Res. ADD10 ADDR ALERT Bit 15 SMBALERT: SMBus Alert In SMBus host mode: 0: no SMBAlert 1: SMBAlert event occurred on pin In SMBus slave mode: 0: no SMBAlert response address header 1: SMBAlert response address header to SMBAlert LOW received... - Page 341 RM0008 Inter-integrated circuit (I2C) interface Bit 10 AF: Acknowledge Failure. 0: No acknowledge failure 1: Acknowledge failure – Set by hardware when no acknowledge is returned. – Cleared by software writing 0, or by hardware when PE=0. Bit 9 ARLO: Arbitration Lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master...
- Page 342 Inter-integrated circuit (I2C) interface RM0008 Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
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Page 343: Status Register 2 (I2C_Sr2)
RM0008 Inter-integrated circuit (I2C) interface 15.7.7 Status register 2 (I2C_SR2) Address offset: 0x18 Reset value:0x0000 PEC[7:0] DUALF Res. BUSY HOST CALL AULT Bits 15:8 PEC[7:0] Packet Error Checking Register This register contains the internal PEC when ENPEC=1. Bit 7 DUALF: Dual Flag (Slave mode) 0: Received address matched with OAR1 1: Received address matched with OAR2 –... -
Page 344: Clock Control Register (I2C_Ccr)
Inter-integrated circuit (I2C) interface RM0008 Bit 0 MSL: Master/Slave 0: Slave Mode 1: Master Mode – Set by hardware as soon as the interface is in Master mode (SB=1). – Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1), or by hardware when PE=0. -
Page 345: Trise Register (I2C_Trise)
RM0008 Inter-integrated circuit (I2C) interface 15.7.9 TRISE Register (I2C_TRISE) Address offset: 0x20 Reset value: 0x0002 Reserved TRISE[5:0] Bits 15:6 Reserved, forced by hardware to 0. Bits 5:0 TRISE[5:0]: Maximum Rise Time in Fast/Standard mode (Master mode) These bits must be programmed with the maximum SCL rise time given in the I C bus specification, incremented by 1. -
Page 346: I2C Register Map
Inter-integrated circuit (I2C) interface RM0008 15.8 C register map Table 47. C register map and reset values Offset Register I2C_CR1 Reserved Reset value I2C_CR2 FREQ[5:0] Reserved Reset value I2C_OAR1 ADD[9:8] ADD[7:1] Reserved Reserved Reset value I2C_OAR2 ADD2[7:1] Reserved Reset value I2C_DR DR[7:0] Reserved... -
Page 347: Analog-To-Digital Converter (Adc)
RM0008 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) 16.1 Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from 16 external and two internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. -
Page 348: Figure 141. Single Adc Block Diagram
Analog-to-digital converter (ADC) RM0008 Figure 141. Single ADC block diagram Interrupt Flags enable bits End of Conversion EOCIE ADC Interrupt to NVIC End of Injected Conversion JEOC JEOCIE Analog Watchdog Event AWDIE ANALOG WATCHDOG Compare Result High Threshold (12 bits) Low Threshold (12 bits) INJECTED DATA REGISTERS REF+... -
Page 349: Pin Description
RM0008 Analog-to-digital converter (ADC) 16.3 Pin description Table 48. ADC pins Name Signal type Remarks The higher/positive reference voltage for the ADC, Input, analog reference ≤ ≤ REF+ positive 2.4 V REF+ Analog power supply equal to V Input, analog supply ≤... -
Page 350: Single Conversion Mode
Analog-to-digital converter (ADC) RM0008 If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the new chosen group. Temperature sensor/V internal channels REFINT The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage V... -
Page 351: Analog Watchdog
RM0008 Analog-to-digital converter (ADC) Figure 142. Timing diagram ADC_CLK SET ADON Start 1st conversion Start next conversion ADC power on ADC Conversion Next ADC Conversion STAB Conversion Time (total conv time) Software resets EOC bit 16.4.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. -
Page 352: Scan Mode
Analog-to-digital converter (ADC) RM0008 Table 49. Analog watchdog channel selection (continued) ADC_CR1 register control bits (x = don’t care) Channels to be guarded by Analog Watchdog AWDSGL bit AWDEN bit JAWDEN bit Single injected channel Single regular channel Single regular or injected channel 1. -
Page 353: Injected Channel Management
RM0008 Analog-to-digital converter (ADC) 16.4.9 Injected channel management Triggered injection To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the ADC_CR1 register. Start conversion of a group of regular channels either by external trigger or by setting the ADON bit in the ADC_CR2 register. -
Page 354: Discontinuous Mode
Analog-to-digital converter (ADC) RM0008 16.4.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of conversions selected in the ADC_SQRx registers. -
Page 355: Calibration
RM0008 Analog-to-digital converter (ADC) 16.5 Calibration The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy errors due to internal capacitor bank variations. During calibration, an error-correction code (digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code. -
Page 356: Data Alignment
Analog-to-digital converter (ADC) RM0008 16.6 Data alignment ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion. Data can be left or right aligned as shown in Figure 146. Figure 147. The injected group channels converted data value is decreased by the user-defined offset written in the ADC_JOFRx registers so the result can be a negative value. -
Page 357: Dma Request
RM0008 Analog-to-digital converter (ADC) Table 50. External trigger for regular channels Source Type EXTSEL[2:0] Timer 1 CC1 output Timer 1 CC2 output Timer 1 CC3 output Internal signal from on-chip timers Timer 2 CC2 output Timer 3 TRGO output Timer 4 CC4 output EXTI line11 External pin SWSTART... -
Page 358: Dual Adc Mode
Analog-to-digital converter (ADC) RM0008 16.10 Dual ADC mode In devices with two ADCs, dual ADC mode can be used (see Figure 148). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register. -
Page 359: Figure 148. Dual Adc Block Diagram
RM0008 Analog-to-digital converter (ADC) Figure 148. Dual ADC block diagram Regular data register (12 bits) (16 bits) Injected data registers (4 x 16 bits) Regular ADC2 (Slave) channels injected channels internal triggers Regular data register (16 bits)* Injected data registers (4 x 16 bits) ADCx_IN0 Regular... -
Page 360: Injected Simultaneous Mode
Analog-to-digital converter (ADC) RM0008 16.10.1 Injected simultaneous mode This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits ADC1_CR2 in the register). A simultaneous trigger is provided to ADC2. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). -
Page 361: Fast Interleaved Mode
RM0008 Analog-to-digital converter (ADC) Figure 150. Regular simultaneous mode on 16 channels Sampling Conversion ADC1 CH15 ADC2 CH15 CH14 CH13 CH12 End of conversion on ADC1 and ADC2 Trigger 16.10.3 Fast interleaved mode This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1. -
Page 362: Alternate Trigger Mode
Analog-to-digital converter (ADC) RM0008 After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. -
Page 363: Independent Mode
RM0008 Analog-to-digital converter (ADC) If the injected discontinuous mode is enabled for both ADC1 and ADC2: When the 1st trigger occurs, the first injected channel in ADC1 is converted. When the 2nd trigger arrives, the first injected channel in ADC2 are converted and so on.. -
Page 364: Combined Injected Simultaneous + Interleaved
Analog-to-digital converter (ADC) RM0008 Figure 155. Alternate + Regular simultaneous 1st trig ADC1 reg ADC1 inj ADC2 reg ADC2 inj synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored. -
Page 365: Temperature Sensor
RM0008 Analog-to-digital converter (ADC) 16.11 Temperature sensor The temperature sensor can be used to measure the ambient temperature (T ) of the device. The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sampling time for temperature sensor analog input must be greater than 2.2 µs. -
Page 366: Interrupts
Analog-to-digital converter (ADC) RM0008 Reading the temperature To use the sensor: Select the ADCx_IN16 input channel. Select a sample time greater than 2.2 µs Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. Start the ADC conversion by setting the ADON bit (or by external trigger). -
Page 367: Adc Register Description
RM0008 Analog-to-digital converter (ADC) 16.13 ADC register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 16.13.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved Reserved STRT JSTRT JEOC Bits 31:5 Reserved, must be kept cleared. -
Page 368: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0008 16.13.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 Reserved Reserved DUALMOD[3:0] DISC DISC JAUT JEOC DISCNUM[2:0] SCAN AWDIE EOCIE AWDCH[4:0] Bits 31:24 Reserved, must be kept cleared. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software. - Page 369 RM0008 Analog-to-digital converter (ADC) Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels.
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Page 370: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0008 Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog Watchdog. 00000: ADC analog input Channel0 00001: ADC analog input Channel1 .. - Page 371 RM0008 Analog-to-digital converter (ADC) Bit 20 EXTTRIG: External Trigger Conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External Event Select for regular group These bits select the external event used to trigger the start of conversion of a regular group:...
- Page 372 Analog-to-digital converter (ADC) RM0008 Bit 3 RSTCAL: Reset Calibration This bit is set by software and cleared by hardware. It is cleared after the calibration registers are initialized. 0: Calibration register initialized. 1: Initialize calibration register. Note: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the calibration registers.
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Page 373: Adc Sample Time Register 1 (Adc_Smpr1)
RM0008 Analog-to-digital converter (ADC) 16.13.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 Reserved SMP17[2:0] SMP16[2:0] SMP15[2:1] SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] 15_0 Bits 31:24 Reserved, must be kept cleared. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. -
Page 374: Adc Sample Time Register 2 (Adc_Smpr2)
Analog-to-digital converter (ADC) RM0008 16.13.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. -
Page 375: Adc Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
RM0008 Analog-to-digital converter (ADC) 16.13.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) Address offset: 0x14-0x20 Reset value: 0x0000 0000 Reserved Reserved JOFFSETx[11:0] Bits 31:12 Reserved, must be kept cleared. Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. -
Page 376: Adc Watchdog Low Threshold Register (Adc_Ltr)
Analog-to-digital converter (ADC) RM0008 16.13.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28 Reset value: 0x0000 0000 Reserved Reserved LT[11:0] Bits 31:12 Reserved, must be kept cleared. Bits 11:0 LT[11:0] Analog watchdog low threshold These bits are written by software to define the low threshold for the Analog Watchdog. 16.13.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C... -
Page 377: Adc Regular Sequence Register 2 (Adc_Sqr2)
RM0008 Analog-to-digital converter (ADC) 16.13.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 Reserved SQ12[4:0] SQ11[4:0] SQ10[4:1] SQ10_ SQ9[4:0] SQ8[4:0] SQ7[4:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted. -
Page 378: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0008 16.13.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 Reserved JL[1:0] JSQ4[4:1] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept cleared. Bits 21:20 JL[1:0]: Injected Sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. -
Page 379: Adc Injected Data Register X (Adc_Jdrx) (X= 1
RM0008 Analog-to-digital converter (ADC) 16.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 Reserved JDATA[15:0] Bits 31:16 Reserved, must be kept cleared. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 146 Figure... -
Page 380: Adc Register Map
Analog-to-digital converter (ADC) RM0008 16.14 ADC register map The following table summarizes the ADC registers. Table 53. ADC - register map and reset values Offset Register ADC_SR Reserved Reset value DUALMOD DISC ADC_CR1 AWDCH[4:0] [3:0] NUM [2:0] Reserved Reset value EXTSEL JEXTSEL ADC_CR2... - Page 381 RM0008 Analog-to-digital converter (ADC) Table 53. ADC - register map and reset values (continued) Offset Register ADC_JDR1 JDATA[15:0] Reserved Reset value ADC_JDR2 JDATA[15:0] Reserved Reset value ADC_JDR3 JDATA[15:0] Reserved Reset value ADC_JDR4 JDATA[15:0] Reserved Reset value ADC_DR ADC2DATA[15:0] Regular DATA[15:0] Reset value Refer to Table 1 on page 27...
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Page 382: Usb Full Speed Device Interface (Usb)
USB full speed device interface (USB) RM0008 USB full speed device interface (USB) 17.1 Introduction The USB peripheral implements an interface between a full-speed USB 2.0 bus and the APB1 bus. USB suspend/resume are supported which allows to stop the device clocks for low-power consumption. -
Page 383: Functional Description
RM0008 USB full speed device interface (USB) Figure 159. USB peripheral block diagram USB Clock (48MHz) Analog Transceiver PCLK1 Control Clock RX-TX registers & logic Recovery Suspend Timer Control Endpoint Interrupt Selection registers & logic S.I.E. Packet Buffer Endpoint Endpoint Interface Registers Registers... -
Page 384: Description Of Usb Blocks
USB full speed device interface (USB) RM0008 When a token for a valid function/endpoint pair is recognized by the USB peripheral, the related data transfer (if required and if the endpoint is configured) takes place. The data buffered by the USB peripheral is loaded in an internal 16 bit register and memory access to the dedicated buffer is performed. -
Page 385: Programming Considerations
RM0008 USB full speed device interface (USB) endpoints* in any combination. For example the USB peripheral can be programmed to have 4 double buffer endpoints and 8 single-buffer/mono-directional endpoints. Control Registers: These are the registers containing information about the status of the whole USB peripheral and used to force some USB events, such as resume and power-down. - Page 386 USB full speed device interface (USB) RM0008 As a first step application software needs to activate register macrocell clock and de-assert macrocell specific reset signal using related control bits provided by device clock management logic. After that, the analog part of the device related to the USB transceiver must be switched on using the PDWN bit in CNTR register, which requires a special handling.
- Page 387 RM0008 USB full speed device interface (USB) Note: Due to USB data rate and packet memory interface requirements, the APB1 clock frequency must be greater than 8 MHz to avoid data overrun/underrun problems. Each endpoint is associated with two packet buffers (usually one for transmission and the other one for reception).
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Page 388: Figure 160. Packet Buffer Areas With Examples Of Buffer Description Table Locations
USB full speed device interface (USB) RM0008 Figure 160. Packet buffer areas with examples of buffer description table locations Buffer for double-buffered IN Endpoint 3 0001_1110 (1E) COUNT3_TX_1 0001_1100 (1C) ADDR3_TX_1 0001_1010 (1A) COUNT3_TX_0 Buffer for double-buffered 0001_1000 (18) ADDR3_TX_0 OUT Endpoint 2 0001_0110 (16) COUNT2_RX_1... - Page 389 RM0008 USB full speed device interface (USB) Endpoint initialization The first step to initialize an endpoint is to write appropriate values to the ADDRn_TX/ADDRn_RX registers so that the USB peripheral finds the data to be transmitted already available and the data to be received can be buffered. The EP_TYPE bits in the register must be set according to the endpoint type, eventually using the EP_KIND bit to enable any special required feature.
- Page 390 USB full speed device interface (USB) RM0008 OUT and SETUP packets (data reception) These two tokens are handled by the USB peripheral more or less in the same way; the differences in the handling of SETUP packets are detailed in the following paragraph about control transfers.
- Page 391 RM0008 USB full speed device interface (USB) Control transfers Control transfers are made of a SETUP transaction, followed by zero or more data stages, all of the same direction, followed by a status stage (a zero-byte transfer in the opposite direction).
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Page 392: Double-Buffered Endpoints
USB full speed device interface (USB) RM0008 17.5.3 Double-buffered endpoints All different endpoint types defined by the USB standard represent different traffic models, and describe the typical requirements of different kind of data transfer operations. When large portions of data are to be transferred between the host PC and the USB function, the bulk endpoint type is the most suited model. -
Page 393: Table 54. Double-Buffering Buffer Flag Definition
RM0008 USB full speed device interface (USB) Table 54. Double-buffering buffer flag definition Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint DTOG DTOG_TX (bit 6) DTOG_RX (bit 14) SW_BUF bit 14 bit 6 The memory buffer which is currently being used by the USB peripheral is defined by DTOG buffer flag, while the buffer currently in use by application software is identified by SW_BUF buffer flag. -
Page 394: Isochronous Transfers
USB full speed device interface (USB) RM0008 be masked as ‘10’ (NAK) when a buffer conflict between the USB peripheral and the application software is detected (this condition is identified by DTOG and SW_BUF having the same value, see Table 55 on page 393). -
Page 395: Suspend/Resume Events
RM0008 USB full speed device interface (USB) Table 56. Isochronous memory buffers usage (continued) Endpoint DTOG bit Packet buffer used by the Packet buffer used by the Type value USB peripheral application software ADDRn_RX_0 / COUNTn_RX_0 ADDRn_RX_1 / COUNTn_RX_1 buffer description table buffer description table locations. -
Page 396: Table 57. Resume Event Detection
USB full speed device interface (USB) RM0008 reception is disabled to avoid any further SUSP interrupts being issued while the USB is suspended. Remove or reduce any static power consumption in blocks different from the USB peripheral. Set LP_MODE bit in register to 1 to remove static power consumption in the analog USB transceivers but keeping them able to detect resume activity. -
Page 397: Usb Register Description
RM0008 USB full speed device interface (USB) completed by the host PC and its end can be monitored again using the RXDP and RXDM bits in the register. Note: The RESUME bit must be anyway used only after the USB peripheral has been put in suspend mode, setting the FSUSP bit in register to 1. - Page 398 USB full speed device interface (USB) RM0008 Bit 12 WKUPM: Wakeup Interrupt Mask 0: WKUP Interrupt disabled. 1: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the register is set. Bit 11 SUSPM: Suspend mode Interrupt Mask 0: Suspend Mode Request (SUSP) Interrupt disabled.
- Page 399 RM0008 USB full speed device interface (USB) Bit 0 FRES: Force USB Reset 0: Clear USB reset. 1: Force a reset of the USB peripheral, exactly like a RESET signalling on the USB. The USB peripheral is held in RESET state until software clears this bit. A “USB-RESET” interrupt is generated, if enabled.
- Page 400 USB full speed device interface (USB) RM0008 Bit 15 CTR: Correct Transfer This bit is set by the hardware to indicate that an endpoint has successfully completed a transaction; using DIR and EP_ID bits software can determine which endpoint requested the interrupt. This bit is read-only.
- Page 401 RM0008 USB full speed device interface (USB) Bit 9 SOF: Start Of Frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1mS synchronization event to the USB host and to safely read the register which is updated at the SOF packet reception (this could be useful for isochronous applications).
- Page 402 USB full speed device interface (USB) RM0008 USB frame number register () Address offset: 0x48 Reset value: 0x0XXX where X is undefined RXDP RXDM LSOF[1:0] FN[10:0] Bit 15 RXDP: Receive Data + Line Status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event.
- Page 403 RM0008 USB full speed device interface (USB) USB device address () Address offset: 0x4C Reset value: 0x0000 Reserved ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Res. Bits 15:8 Reserved Bit 7 EF: Enable Function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits.
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Page 404: Endpoint-Specific Registers
USB full speed device interface (USB) RM0008 17.6.2 Endpoint-specific registers The number of these registers varies according to the number of endpoints that the USB peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional endpoints. Each USB device must support a control endpoint whose address (EA bits) must be set to 0. - Page 405 RM0008 USB full speed device interface (USB) Bit 14 DTOG_RX: Data Toggle, for reception transfers If the endpoint is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent to the USB host, following a data packet reception having a matching data PID value;...
- Page 406 USB full speed device interface (USB) RM0008 Bit 8 EP_KIND: Endpoint Kind The meaning of this bit depends on the endpoint type configured by the EP_TYPE bits. Table 60 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint.
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Page 407: Buffer Descriptor Table
RM0008 USB full speed device interface (USB) Table 58. Reception status encoding STAT_RX[1:0] Meaning DISABLED: all reception requests addressed to this endpoint are ignored. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. NAK: the endpoint is naked and all reception requests result in a NAK handshake. VALID: this endpoint is enabled for reception. - Page 408 USB full speed device interface (USB) RM0008 address must be multiplied by two. The first packet memory location is located at 0x4000 6000. The buffer descriptor table entry associated with the USB_EPnR registers is described below. A thorough explanation of packet buffers and the buffer descriptor table usage can be found Structure and usage of packet buffers on page 386.
- Page 409 RM0008 USB full speed device interface (USB) Transmission byte count n () Address offset: [USB_BTABLE] + n*16 + 4 USB local Address: [USB_BTABLE] + n*8 + 2 COUNTn_TX[9:0] Bits 15:10 These bits are not used since packet size is limited by USB specifications to 1023 bytes. Their value is not considered by the USB peripheral.
- Page 410 USB full speed device interface (USB) RM0008 Reception byte count n () Address offset: [USB_BTABLE] + n*16 + 12 USB local Address: [USB_BTABLE] + n*8 + 6 BLSIZE NUM_BLOCK[4:0] COUNTn_RX[9:0] This table location is used to store two different values, both required during packet reception.
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Page 411: Table 62. Definition Of Allocated Buffer Memory
RM0008 USB full speed device interface (USB) Table 62. Definition of allocated buffer memory Value of Memory allocated Memory allocated NUM_BLOCK[4:0] when BL_SIZE=0 when BL_SIZE=1 0 (‘00000’) Not allowed 32 bytes 1 (‘00001’) 2 bytes 64 bytes 2 (‘00010’) 4 bytes 96 bytes 3 (‘00011’) 6 bytes... -
Page 412: Usb Register Map
USB full speed device interface (USB) RM0008 17.7 USB Register map Table 63. USB register map and reset values Offset Register STAT_ STAT_ USB_EP0R TYPE EA[3:0] Reserved [1:0] [1:0] [1:0] Reset value STAT_ STAT_ USB_EP1R TYPE EA[3:0] Reserved [1:0] [1:0] [1:0] Reset value STAT_... -
Page 413: Serial Peripheral Interface (Spi)
RM0008 Serial peripheral interface (SPI) Serial peripheral interface (SPI) 18.1 Introduction The serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial communication with external devices. The interface can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multimaster configuration. -
Page 414: Functional Description
Serial peripheral interface (SPI) RM0008 18.3 Functional description 18.3.1 General description The block diagram of the SPI is shown in Figure 161. Figure 161. SPI block diagram Address and data bus Read RX buffer SPI_CR2 MOSI RXNE TXDM RXDM SSOE SHIFT register MISO LsbFirst... -
Page 415: Figure 162. Single Master/ Single Slave Application
RM0008 Serial peripheral interface (SPI) Figure 162. Single master/ single slave application Slave Master MSBit LSBit MSBit LSBit MISO MISO 8-bit shift register 8-bit shift register MOSI MOSI clock generator Not used if NSS is managed by software Note: Here, the NSS pin is configured as input The MOSI pins are connected together and the MISO pins are connected together. - Page 416 Serial peripheral interface (SPI) RM0008 If CPHA (clock phase) bit is set, the second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the first clock transition.
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Page 417: Spi Slave Mode
RM0008 Serial peripheral interface (SPI) Figure 164. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 MISO LSBit MSBit (from master) 8 or 16 bits depending on Data Frame Format (see SPI_CR1) MOSI LSBit MSBit (from slave) (to slave) Capture strobe CPHA =0... -
Page 418: Spi Master Mode
Serial peripheral interface (SPI) RM0008 Procedure Set the DFF bit to define 8- or 16-bit data frame format Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 164). -
Page 419: Simplex Communication
RM0008 Serial peripheral interface (SPI) SSM and SSI bits in the SPI_CR1 register. If the NSS pin is required in output mode, just the SSOE bit should be set. The MSTR and SPE bits must be set (they remain set only if the NSS pin is connected to a high level signal). -
Page 420: Status Flags
Serial peripheral interface (SPI) RM0008 and the current reception terminates. In slave mode, the SPI will continue to receive as long as the NSS is pulled down (or the SSI bit is reset) and the SCK is running. Note: The SPI can be used in Tx-only mode when the RXONLY bit in the SPI_CR1 register is reset, the RX pin (MISO in master or MOSI in slave) can be used as GPIO. -
Page 421: Spi Communication Using Dma (Direct Memory Addressing)
RM0008 Serial peripheral interface (SPI) If data are present in the TX buffer, the CRC value is transmitted only after the transmission of the data byte. During CRC transmission, the CRC calculator is switched off and the register value remains unchanged. Note: Please refer to the product specifications for availability of this feature. -
Page 422: Error Flags
Serial peripheral interface (SPI) RM0008 18.3.8 Error flags Master mode fault (MODF) Master mode fault occurs when the master device has its NSS pin pulled low (in hardware mode) or SSI bit low (in software mode), this automatically sets the MODF bit. Master mode fault affects the SPI peripheral in the following ways: The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set. -
Page 423: Interrupts
RM0008 Serial peripheral interface (SPI) 18.3.9 Interrupts Table 64. SPI interrupt requests Interrupt event Event flag Enable Control bit Transmit buffer empty flag TXEIE Receive buffer not empty flag RXNE RXNEIE Master Mode fault event MODF Overrun error ERRIE CRC error flag CRCERR 18.4 SPI register description... - Page 424 Serial peripheral interface (SPI) RM0008 Bit 11 DFF: Data Frame Format 0: 8-bit data frame format is selected for transmission/reception 1: 16-bit data frame format is selected for transmission/reception Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation Bit 10 RXONLY: Receive only This bit combined with BIDImode bit selects the direction of transfer in 2 line unidirectional mode.
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Page 425: Spi Control Register 2 (Spi_Cr2)
RM0008 Serial peripheral interface (SPI) 18.4.2 SPI control register 2 (SPI_CR2) Address offset: 0x04 Reset value: 0000 0000 (0x0000) RXNE TXDMA RXDMA Reserved TXEIE ERRIE Reserved SSOE Bits 15:8 Reserved. Forced to 0 by hardware. Bit 7 TXEIE: Tx buffer empty interrupt enable 0: TXE interrupt masked 1: TXE interrupt not masked. -
Page 426: Spi Status Register (Spi_Sr)
Serial peripheral interface (SPI) RM0008 18.4.3 SPI status register (SPI_SR) Address offset: 0x08 Reset value: 0000 0010 (0x0002) Reserved MODF Reserved RXNE Bits 15:8 Reserved. Forced to 0 by hardware. Bit 7 BSY: Busy flag 0: SPI not busy 1: SPI is busy in communication or Tx buffer is not empty This flag is set and reset by hardware. -
Page 427: Spi Data Register (Spi_Dr)
RM0008 Serial peripheral interface (SPI) 18.4.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0000 0000 (0x0000) DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer). -
Page 428: Spi Rx Crc Register (Spi_Rxcrcr)
Serial peripheral interface (SPI) RM0008 18.4.6 SPI Rx CRC register (SPI_RXCRCR) Address offset: 0x14 Reset value: 0000 0000 (0x0000) RxCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC Register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. -
Page 429: Spi Register Map
RM0008 Serial peripheral interface (SPI) 18.5 SPI register map Table 65. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] Reserved Reset value SPI_CR2 Reserved Reset value SPI_SR Reserved Reset value SPI_DR DR[15:0] Reserved Reset value SPI_CRCPR CRCPOLY[15:0] Reserved Reset value SPI_RXCRCR... -
Page 430: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Universal synchronous asynchronous receiver transmitter (USART) 19.1 Introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate generator. -
Page 431: General Description
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Parity control: – Transmits parity bit – Checks parity of received data byte Four error detection flags: – Overrun error – Noise error – Frame error – Parity error Ten interrupt sources with flags: –... - Page 432 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: An Idle Line prior to transmission or reception A start bit A data word (8 or 9 bits) least significant bit first 0.5,1, 1.5, 2 Stop bits indicating that the frame is complete This interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit fraction...
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Page 433: Block Diagram
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 19.3.1 Block diagram Figure 165. USART block diagram PRDATA PWDATA Write Read (DATA REGISTER) DR (CPU or DMA) (CPU or DMA) Receive Data Register (RDR) Transmit Data Register (TDR) IrDA SW_RX ENDEC Receive Shift Register Transmit Shift Register BLOCK IRDA_OUT... -
Page 434: Usart Character Description
Universal synchronous asynchronous receiver transmitter (USART) RM0008 19.3.2 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 166). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”... -
Page 435: Transmitter
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 19.3.3 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin. -
Page 436: Figure 167. Configurable Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 167. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next Data Frame Parity Data Frame Next Start Start Stop Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible... -
Page 437: Receiver
RM0008 Universal synchronous asynchronous receiver transmitter (USART) When no transmission is taking place, a write instruction to the USART_DR register places the data directly in the shift register, the data transmission starts, and the TXE bit is immediately set. When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt is generated if the TCIE is set in the USART_CR1 register. - Page 438 Universal synchronous asynchronous receiver transmitter (USART) RM0008 When a character is received The RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags).
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Page 439: Table 66. Noise Detection From Sampled Data
RM0008 Universal synchronous asynchronous receiver transmitter (USART) when the new data is received during the reading sequence (between the USART_SR register read access and the USART_DR read access). Noise error Over-sampling techniques are used (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise. -
Page 440: Fractional Baud Rate Generation
Universal synchronous asynchronous receiver transmitter (USART) RM0008 When the framing error is detected: The FE bit is set by hardware The invalid data is transferred from the Shift register to the USART_DR register. No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. -
Page 441: Table 67. Error Calculation For Programmed Baud Rates
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Fraction (USARTDIV) = 12/16 = 0.75d Therefore USARTDIV = 27.75d Example 2: To program USARTDIV = 25.62d, This leads to: DIV_Fraction = 16*0.62d = 9.92d, nearest real number 10d = 0xA DIV_Mantissa = mantissa (25.620d) = 25d = 0x19 Then, USART_BRR = 0x19A Example 3: To program USARTDIV = 50.99d... -
Page 442: Multiprocessor Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Note: The lower the CPU clock the lower will be the accuracy for a particular Baud rate. The upper limit of the achievable baud rate can be fixed with this data. Only USART1 is clocked with PCLK2 (72 MHz Max). Other USARTs are clocked with PCLK1 (36 MHz Max). -
Page 443: Parity Control
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Address mark detection (WAKE=1) In this mode, bytes are recognized as addresses if their MSB is a ‘1’ else they are considered as data. In an address byte, the address of the targeted receiver is put on the 4 LSB. -
Page 444: Lin (Local Interconnection Network) Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Ex: data=00110101;... -
Page 445: Figure 171. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) detection circuit receives either a ‘1’, if the break word was not complete, or a delimiter character if a break has been detected. The behavior of the break detector state machine and the break flag is shown on the Figure 171: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 445. -
Page 446: Usart Synchronous Mode
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 172. Break detection in LIN mode vs. Framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK... -
Page 447: Figure 173. Usart Example Of Synchronous Transmission
RM0008 Universal synchronous asynchronous receiver transmitter (USART) has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. -
Page 448: Single Wire Half Duplex Communication
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 175. USART data clock timing diagram (M=1) Idle or preceding Start transmission M=1 (9 data bits) Idle or next Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop... -
Page 449: Smartcard
RM0008 Universal synchronous asynchronous receiver transmitter (USART) arbiter, for instance). In particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TE bit is set. 19.3.11 Smartcard The smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. -
Page 450: Figure 178. Parity Error Detection Using The 1.5 Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0008 NACK signal (pulling transmit line low for 1 baud clock) will cause a framing error on the transmitter side (configured with 1.5 stop bits). The application can handle re-sending of data according to the protocol. A parity error is ‘NACK’ed by the receiver if the NACK control bit is set, otherwise a NACK is not transmitted. -
Page 451: Irda Sir Endec Block
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 19.3.12 IrDA SIR ENDEC block The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode, the following bits must be kept cleared: LINEN, STOP and CLKEN bits in the USART_CR2 register, SCEN and HDSEL bits in the USART_CR3 register. -
Page 452: Continuous Communication Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Receiver: Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in USART_GTPR). - Page 453 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the DMA specification) to the USART_DR register whenever the TXE bit is set.
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Page 454: Hardware Flow Control
Universal synchronous asynchronous receiver transmitter (USART) RM0008 case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in the USART_CR3 register), which if set will issue an interrupt after the current byte with either of these errors. 19.3.14 Hardware flow control It is possible to control the serial data flow between 2 devices by using the nCTS input and... -
Page 455: Figure 183. Cts Flow Control
RM0008 Universal synchronous asynchronous receiver transmitter (USART) When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure below shows an example of communication with CTS flow control enabled. -
Page 456: Interrupt Requests
Universal synchronous asynchronous receiver transmitter (USART) RM0008 19.4 Interrupt requests Table 69. USART interrupt requests Enable Interrupt event Event flag Control bit Transmit Data Register Empty TXEIE CTS flag CTSIE Transmission Complete TCIE Received Data Ready to be Read RXNE RXNEIE Overrun Error Detected Idle Line Detected... -
Page 457: Usart Register Description
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 19.5 USART register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 19.5.1 Status register (USART_SR) Address offset: 0x00 Reset value: 0x00C0 Reserved Reserved RXNE IDLE Bits 31:10 Reserved, forced by hardware to 0. - Page 458 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Bit 4 IDLE: IDLE line detected. This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the IDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the USART_DR register).
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Page 459: Data Register (Usart_Dr)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 19.5.2 Data register (USART_DR) Address offset: 0x04 Reset value: Undefined Reserved Reserved DR[8:0] Bits 31:9 Reserved, forced by hardware to 0. Bits 8:0 DR[8:0]: Data value. Contains the Received or Transmitted data character, depending on whether it is read from or written to. -
Page 460: Control Register 1 (Usart_Cr1)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 19.5.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 Reserved RXNE Reserved WAKE PEIE TXEIE TCIE IDLEIE Bits 31:14 Reserved, forced by hardware to 0. Bit 13 UE: USART Enable. When this bit is cleared the USART prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption. - Page 461 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 7 TXEIE: TXE Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An USART interrupt is generated whenever TXE=1 in the USART_SR register Bit 6 TCIE: Transmission Complete Interrupt Enable. This bit is set and cleared by software.
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Page 462: Control Register 2 (Usart_Cr2)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 19.5.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 Reserved Res. LINEN STOP[1:0] CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0] Bits 31:15 Reserved, forced by hardware to 0. Bit 14 LINEN: LIN mode enable This bit is set and cleared by software. - Page 463 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 LBCL: Last Bit Clock pulse. This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the SCLK pin.
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Page 464: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 19.5.6 Control register 3 (USART_CR3) Address offset: 0x14 Reset value: 0x0000 Reserved Reserved CTSIE CTSE RTSE DMAT DMAR SCEN NACK IRLP IREN Bits 31:11 Reserved, forced by hardware to 0. Bit 10 CTSIE: CTS Interrupt Enable. 0: Interrupt is inhibited 1: An interrupt is generated whenever CTS=1 in the USART_SR register Bit 9 CTSE: CTS Enable. - Page 465 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 4 NACK: Smartcard NACK enable. 0: NACK transmission in case of parity error is disabled 1: NACK transmission during parity error is enabled. Bit 3 HDSEL: Half-Duplex Selection. Selection of Single-wire Half-duplex mode 0: Half duplex mode is not selected 1: Half duplex mode is selected Bit 2 IRLP: IrDA Low-Power.
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Page 466: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 19.5.7 Guard time and prescaler register (USART_GTPR) Address offset: 0x18 Reset value: 0x0000 Reserved GT[7:0] PSC[7:0] Bits 31:16 Reserved, forced by hardware to 0. Bits 15:8 GT[7:0]: Guard time value. This bit-field gives the Guard time value in terms of number of baud clocks. This is used in Smartcard mode. -
Page 467: Usart Register Map
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 19.6 USART register map Table 70. USART register map and reset values Offset Register USART_SR Reserved Reset value USART_DR DR[8:0] Reserved Reset value DIV_Fraction USART_BRR DIV_Mantissa[15:4] [3:0] Reserved Reset value USART_CR1 Reserved Reset value STOP USART_CR2 ADD[3:0]... -
Page 468: Debug Support (Dbg)
Debug support (DBG) RM0008 Debug support (DBG) 20.1 Overview The STM32F10xxx is built around a Cortex-M3 core which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s internal state and the system’s external state may be examined. -
Page 469: Referenced Arm Documentation
RM0008 Debug support (DBG) The ARM Cortex-M3 core provides integrated on-chip debug support. It is comprised of: SWJ-DP: Serial wire / JTAG debug port AHP-AP: AHB access p ITM: Instrumentation trace macrocell FPB: Flash patch breakpoint DWT: Data watchpoint trigger TPUI: Trace port unit interface (available on larger packages, where the corresponding pins are mapped) It also includes debug features dedicated to STM32F10xxx:... -
Page 470: Mechanism To Select The Jtag-Dp Or The Sw-Dp
Debug support (DBG) RM0008 Figure 186. SWJ debug port (asynchronous trace) TRACESWO SWJ-DP JTDO JTDI nTRST JNTRST nTRST JTAG-DP nPOTRST From SWD/JTAG power-on select nPOTRST reset DBGRESETn SWDITMS DBGDI JTMS/SWDIO SWDO DBGDO SW-DP SWDOEN DBGDOEN SWCLKTCK JTCK/SWCLK DBGCLK Figure 186 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with TDO. -
Page 471: Pinout And Debug Port Pins
RM0008 Debug support (DBG) 20.4 Pinout and debug port pins The STM32F10xxx MCU is available in various packages with different numbers of available pins. As a result, some functionality related to pin availability may differ between packages. 20.4.1 SWJ debug port pins Five pins are used as outputs from the STM32F10xxx for the SWJ-DP as alternate functions of General Purpose I/Os. -
Page 472: Internal Pull-Up And Pull-Down On Jtag Pins
Debug support (DBG) RM0008 Table 72. Flexible SWJ-DP pin assignment SWJ I/O pin assigned SWJ_ PA13 / PA14 / Available debug ports PA15 / PB3 / PB4/ JTMS/ JTCK/ [2:0] JTDI JTDO JNTRST SWDIO SWCLK Full SWJ (JTAG-DP + SW-DP) - Reset State Full SWJ (JTAG-DP + SW-DP) but without JNTRST... -
Page 473: Using Serial Wire And Releasing The Unused Debug Pins As Gpios
RM0008 Debug support (DBG) 20.4.4 Using serial wire and releasing the unused debug pins as GPIOs To use the serial wire DP to release some GPIOs, the user software must set SWJ_CFG=010 just after reset. This release PA15, PB3 and PB4 which now become available as GPIOs. -
Page 474: Id Codes And Locking Mechanism
20.6.1 MCU device ID code The MCU STM32F10xxx integrates an MCU ID code. This ID identifies the ST MCU part- number and the die revision. It is part of the DBG_MCU Component and is mapped on the external PPB bus (see Section 20.15 on page... -
Page 475: Tmc Tap
RM0008 Debug support (DBG) Bits 31:16 REV_ID(15:0) Revision Identifier This field indicates the revision of the device: 0x0000 = Revision A 0x2000 = Revision B 0x2001 = Revision Z Bits 27:12 Reserved Bits 11:0 DEV_ID(11:0): Device Identifier This field indicates the device. For STM32F10xxx MCU, the device ID is 0x410. 20.6.2 TMC TAP JTAG ID code... -
Page 476: Table 74. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2]
Debug support (DBG) RM0008 Table 73. JTAG debug port data registers IR(3:0) Data register Details Debug Port Access Register This initiates a debug port and allows access to a debug port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request Bits 2:1 = A[3:2] = 2-bit address of a debug port register. -
Page 477: Sw Debug Port
RM0008 Debug support (DBG) Table 74. 32-bit debug port registers addressed through the shifted value A[3:2] Address A(3:2) value Description DP SELECT register: Used to select the current access port and the active 4-words register window. – Bits 31:24: APSEL: select the current AP –... -
Page 478: Sw-Dp State Machine (Reset, Idle States, Id Code)
Debug support (DBG) RM0008 Table 75. Packet request (8-bits) (continued) Name Description A(3:2) Address field of the DP or AP registers (refer to Table Parity Single bit parity of preceding bits Stop Not driven by the host. Must be read as “1” by the target Park because of the pull-up Refer to the Cortex-M3 r1p1 TRM for a detailed description of DPACC and APACC registers. -
Page 479: Dp And Ap Read/Write Accesses
Table 78. SW-DP registers CTRLSEL bit A(3:2) of SELECT Register Notes register The manufacturer code is not set to ST Read IDCODE code. 0x1BA01477 (identifies the SW-DP) Write ABORT Purpose is to: – request a system or debug power-up – configure the transfer operation for AP... -
Page 480: Sw-Ap Registers
Debug support (DBG) RM0008 Table 78. SW-DP registers (continued) CTRLSEL bit A(3:2) of SELECT Register Notes register The purpose is to select the current access Write SELECT port and the active 4-words register window This read buffer is useful because AP accesses are posted (the result of a read AP request is available on the next AP READ... -
Page 481: Core Debug
RM0008 Debug support (DBG) Table 79. Cortex-M3 AHB-AP registers (continued) Address Register name Notes offset 0x0C AHB-AP Data Read/Write 0x10 AHB-AP Banked Data 0 0x14 AHB-AP Banked Data 1 Directly maps the 4 aligned data words without rewriting the Transfer Address Register. 0x18 AHB-AP Banked Data 2 0x1C... -
Page 482: Capability Of The Debugger Host To Connect Under System Reset
Debug support (DBG) RM0008 20.11 Capability of the debugger host to connect under system reset The STM32F10xxx MCU reset system comprises the following reset sources: POR (Power On Reset) which asserts a RESET at each power-up. Internal Watchdog Reset Software Reset External Reset The Cortex-M3 differentiates the reset of the debug part (generally PORRESETn) and the other one (SYSRESETn) -
Page 483: Itm (Instrumentation Trace Macrocell)
RM0008 Debug support (DBG) The DWT also provides some means to give some profiling informations. For this, some counters are accessible to give the number of: Clock cycle Folded instructions Load store unit (LSU) operations Sleep cycles CPI (clock per instructions) Interrupt overhead 20.14 ITM (instrumentation trace macrocell) -
Page 484: Table 81. Main Itm Registers
Debug support (DBG) RM0008 Table 81. Main ITM registers Address Register Details Write 0xC5ACCE55 to unlock Write Access to the other ITM @E0000FB0 ITM Lock Access registers Bits 31-24 = Always 0 Bits 23 = BUSY Bits 22-16 = 7-bits ATB ID which identifies the source of the trace data. -
Page 485: Mcu Debug Component (Mcudbg)
RM0008 Debug support (DBG) 20.15 MCU debug component (MCUDBG) The MCU debug component helps the debugger provide support for: Low-power modes Clock control for timers, watchdog and bxCAN during a breakpoint Control of the trace pins assignment 20.15.1 Debug support for low-power modes To enter low-power mode, the instruction WFI or WFE must be executed. - Page 486 Debug support (DBG) RM0008 DBGMCU_CR Address: 0xE0042004 Only 32-bit access supported POR Reset: 0x00000000 (not reset by system reset) DBG_I2C 2_SMBU Reserved S_TIMEO Res. DBG_I2C DBG_ DBG_ DBG_ DBG_ DBG_ DBG_ DBG_ TRACE_ DBG_ 1_SMBU TRACE_ DBG_ DBG_ CAN_ TIM4_ TIM3_ TIM2_ TIM1_...
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Page 487: Tpiu (Trace Port Interface Unit)
RM0008 Debug support (DBG) Bit 2 DBG_STANDBY: Debug Standby mode 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. From software point of view, exiting from Standby is identical than fetching reset vector (except a few status bit indicated that the MCU is resuming from Standby) 1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active. -
Page 488: Figure 188. Tpiu Block Diagram
Debug support (DBG) RM0008 Figure 188. TPIU block diagram TRACECLKIN Domain CLK Domain TPIU TRACECLKIN TRACECK Asynchronous Trace Out TPIU TRACEDATA Formatter FIFO (serializer) [3:0] TRACESWO External PPB Bus 488/501... -
Page 489: Trace Pin Assignment
RM0008 Debug support (DBG) 20.16.2 TRACE pin assignment Asynchronous mode The asynchronous mode requires 1 extra pin and is available on all packages. It is only available if using Serial Wire mode (not in JTAG mode). Table 82. Asynchronous TRACE pin assignment Trace synchronous mode STM32F10xxx pin TPUI pin name... -
Page 490: Tpui Formatter
Debug support (DBG) RM0008 Table 84. Flexible TRACE pin assignment DBGMCU_CR TRACE I/O pin assigned register PB3 / Pins assigned for: PE2 / PE3 / PE4 / PE5 / PE6 / JTDO/ TRACE TRACE TRACE TRACE TRACE TRACES D[0] D[1] D[2] D[3] No Trace (default... -
Page 491: Tpui Frame Synchronization Packets
RM0008 Debug support (DBG) Note: Refer to the ARM CoreSight Architecture Specification v1.0 (ARM IHI 0029B) for further information Use of the formatter for STM32F10xxx MCU For STM32F10xxx MCU, there is only one TRACE source (the ITM). But the formatter can not be disabled and must be used in bypass mode because the TRACECTL pin is not assigned. -
Page 492: Asynchronous Mode
Debug support (DBG) RM0008 Here, TRACECLKIN is driven internally and is connected to HCLK only when TRACE is used. Note: In this synchronous mode, it is not required to provide a stable clock frequency. The TRACE I/Os (including TRACECK) are driven by the rising edge of TRACLKIN (equal to HCLK). -
Page 493: 20.16.10 Example Of Configuration
RM0008 Debug support (DBG) Table 85. Important TPIU registers Address Register Description Allows the trace port size to be selected: Bit 0: Port size = 1 Bit 1: Port size = 2 0xE0040004 Current port size Bit 2: Port size = 3, not supported Bit 3: Port Size = 4 Only 1 bit must be set. -
Page 494: Dbg Register Map
Debug support (DBG) RM0008 20.17 DBG register map The following table summarizes the Debug registers. Table 86. DBG - register map and reset values Addr. Register DBGMCU_ REV_ID DEV_ID IDCODE Reserved Reset value DBGMCU_CR Reserved Reset value 494/501... -
Page 495: Appendix A Important Notes
RM0008 Important notes Appendix A Important notes The notes listed below apply to STM32F101xx and STM32F103xx devices Revision Z. For more details on how to identify the device Revision, please refer to Section 20.6.1: MCU device ID code on page 474. -
Page 496: Revision History
Revision history RM0008 Revision history Table 87. Document revision history Date Revision Changes Document reference number changed from UM0306 to RM008. The changes below were made with reference to revision 1 of 01-Jun-2007 of UM0306. EXTSEL[2:0] and JEXTSEL[2:0] removed from Table 48: ADC pins on page 349 and V... - Page 497 RM0008 Revision history Table 87. Document revision history (continued) Date Revision Changes Figure 87: Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 Figure 102: Output compare mode, toggle on OC1. modified. CKD definition modified in Section 13.5.1: Control register 1 (TIMx_CR1).
- Page 498 Revision history RM0008 Table 87. Document revision history (continued) Date Revision Changes Figure 165: USART block diagram modified. Procedure modified in Character reception on page 437. Section 19.3.5: Fractional baud rate generation: – Equation legend modified – Table 67: Error calculation for programmed baud rates modified –...
- Page 499 RM0008 Index Index CAN_TDHxR ......305 CAN_TDLxR ......305 ADC_CR1 .
- Page 500 Index RM0008 IWDG_SR ......141 TIM1_CR2 ......190 TIM1_DCR .
- Page 501 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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