ST STM32L4+ Series Reference Manual page 721

RM0432
21.7.3 ADC common regular data register for dual mode (ADC_CDR)
Address offset: 0x0C (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
31 30 29 28
r r r
15 14 13 12
r r r
Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC
Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC.
21.8 ADC register map
The following table summarizes the ADC registers.
Offset
0x000 - 0x0B4
0x0B8 - 0x0FC
0x100 - 0x1B4
0x1B8 - 0x2FC
0x300 - 0x30C
1. Reserved area highlighted in gray.
27 26 25
r r r r
11 10 9
r r r r
In dual mode, these bits contain the regular data of the slave ADC. Refer to
Dual ADC modes.
The data alignment is applied as described in
offset (ADC_DR, OFFSETy, OFFSETy_CH,
In dual mode, these bits contain the regular data of the master ADC. Refer to
Section 21.4.31: Dual ADC
The data alignment is applied as described in
offset (ADC_DR, OFFSETy, OFFSETy_CH,
In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains
MST_ADC_DR[7:0].
Table 141. ADC global register map
24 23 22
RDATA_SLV[15:0]
r r r
8 7 6
RDATA_MST[15:0]
r r r
Section : Data register, data alignment and
ALIGN))
modes.
Section : Data register, data alignment and
ALIGN))
Register
Master ADC1
Reserved
Slave ADC2
Reserved
Master and slave ADCs common registers
RM0432 Rev 6
Analog-to-digital converters (ADC)
21 20 19 18
r r r r
5 4 3 2
r r r r
(1)
17 16
r r
1 0
r r
Section 21.4.31:
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