ST STM32L4+ Series Reference Manual page 303

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Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes

1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single

clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

APB1 peripheral clocks enable in Sleep and Stop modes register 2

(RCC_APB1SMENR2)

Address offset: 0x7C

Reset value: 0x0000 0023

Access: no wait state, word, half-word and byte access

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2SMEN Low power timer 2 clocks enable during Sleep and Stop modes

Bits 4: Reserved, must be kept at reset value.

Bit 1 I2C4SMEN: I2C4 clocks enable during Sleep and Stop modes

Set and cleared by software

Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes

1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single

clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.

Set and cleared by software.

0: TIM2 clocks disabled by the clock gating

1: TIM2 clocks enabled by the clock gating

Set and cleared by software.

0: LPTIM2 clocks disabled by the clock gating

1: LPTIM2 clocks enabled by the clock gating

0: I2C4 clocks disabled by the clock gating

1: I2C4 clocks enabled by the clock gating

Set and cleared by software.

0: LPUART1 clocks disabled by the clock gating

1: LPUART1 clocks enabled by the clock gating

during Sleep and Stop modes

during Sleep and Stop modes

during Sleep and Stop modes

during Sleep and Stop modes

during Sleep and Stop modes

during Sleep and Stop modes

RM0432 Rev 6

Reset and clock control (RCC)

during Sleep and Stop modes

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