ST STM32L4+ Series Reference Manual page 193

RM0432
1. The reset temporization t
5.2.2 Programmable voltage detector (PVD)
You can use the PVD to monitor the V
selected by the PLS[2:0] bits in the
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the
higher or lower than the PVD threshold. This event is internally connected to the EXTI line16
and can generate an interrupt if enabled through the EXTI registers. The rising/falling edge
sensitivity of the EXTI Line16 should be configured according to PVD output behavior i.e. if
the EXTI line 16 is configured to rising edge sensitivity, the interrupt will be generated when
VDD drops below the PVD threshold. As an example the service routine could perform
emergency shutdown tasks.
PVD output
Figure 12. Brown-out reset waveform
V
DD
V (rising edge)
BOR0
Reset
is present only for the BOR lowest threshold (V
RSTTEMPO
Power status register 2
Figure 13. PVD thresholds
V DD
RM0432 Rev 6
hysteresis
Temporization
t
RSTTEMPO
power supply by comparing it to a threshold
DD
Power control register 2
(PWR_SR2), to indicate if V
V threshold
PVD
Power control (PWR)
V (falling edge)
BOR0
).
BOR0
(PWR_CR2).
100 mV
hysteresis
MS31444V5
is
DD
MS31445V2
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