ST STM32L4+ Series Reference Manual page 273

RM0432
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYIE: HSI48 ready interrupt enable
Bit 9 LSECSSIE: LSE clock security system interrupt enable
Bit 8 Reserved, must be kept at reset value.
Bit 7 PLLSAI2RDYIE: PLLSAI2 ready interrupt enable
Bit 6 PLLSAI1RDYIE: PLLSAI1 ready interrupt enable
Bit 5 PLLRDYIE: PLL ready interrupt enable
Bit 4 HSERDYIE: HSE ready interrupt enable
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal HSI48
oscillator.
0: HSI48 ready interrupt disabled
1: HSI48 ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the clock security system
on LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Set and cleared by software to enable/disable interrupt caused by PLLSAI2 lock.
0: PLLSAI2 lock interrupt disabled
1: PLLSAI2 lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by PLSAI1L lock.
0: PLLSAI1 lock interrupt disabled
1: PLLSAI1 lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
RM0432 Rev 6
Reset and clock control (RCC)
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