ST STM32L4+ Series Reference Manual page 436

Chrom-ART Accelerator controller (DMA2D)
13.5.5 DMA2D foreground offset register (DMA2D_FGOR)
Address offset: 0x0010
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 LO[15:0]: Line offset
13.5.6 DMA2D background memory address register (DMA2D_BGMAR)
Address offset: 0x0014
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 MA[31:0]: Memory address
436/2301
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
The line offset used for the foreground image, expressed in pixel when the LOM bit is
reset and in byte when the LOM bit is set.
When expressed in pixels, only LO[13:0] is considered, LO[15:14] are ignored.
This value is used for the address generation. It is added at the end of each line to
determine the starting address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Address of the data used for the background image. This register can only be written
when data transfers are disabled. Once a data transfer has started, this register is read-
only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-
bit per pixel format must be 8-bit aligned.
24 23 22
Res. Res. Res.
8 7 6
LO[15:0]
rw rw rw
24 23 22
MA[31:16]
rw rw rw
8 7 6
MA[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0432
17 16
Res. Res.
1 0
rw rw
17 16
rw rw
1 0
rw rw