ST STM32L4+ Series Reference Manual page 868

Digital filter for sigma delta modulators (DFSDM)
Bits 12:8 JEXTSEL[4:0]: Trigger signal selection for launching injected conversions
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one f
asynchronous trigger has latency 2-3 f
0x00
0x01
...
0x1E
0x1F
Refer to
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group
0: The DMA channel is not enabled to read injected data
1: The DMA channel is enabled to read injected data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 4 JSCAN: Scanning conversion mode for injected conversions
0: One channel conversion is performed from the injected channel group and next the selected
channel from this group is selected.
1: The series of conversions for the injected group channels is executed, starting over with the
lowest selected channel.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
0: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected
conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 2 Reserved, must be kept at reset value.
Bit 1 JSWSTART: Start a conversion of the injected group of channels
0: Writing '0' has no effect.
1: Writing '1' makes a request to convert the channels in the injected conversion group, causing
JCIP to become '1' at the same time. If JCIP=1 already, then writing to JSWSTART has no effect.
Writing '1' has no effect if JSYNC=1.
This bit is always read as '0'.
Bit 0 DFEN: DFSDM_FLTx enable
0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and
all DFSDM_FLTx functions are stopped.
1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating
according to its setting.
Data which are cleared by setting DFEN=0:
–register DFSDM_FLTxISR is set to the reset state
–register DFSDM_FLTxAWSR is set to the reset state
868/2301
DFSDM_FLTx
dfsdm_jtrg0
dfsdm_jtrg1
dfsdm_jtrg30
dfsdm_jtrg31
Table 186: DFSDM triggers
DFSDMCLK
clock cycles (with jitter up to 1 cycle).
DFSDMCLK
connection.
RM0432 Rev 6
clock cycle (with deterministic jitter),
RM0432