ST STM32L4+ Series Reference Manual page 219

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Bit 6 PVME3: Peripheral voltage monitoring 3 enable:

Bit 5 PVME2: Peripheral voltage monitoring 2 enable:

Bit 4 PVME1: Peripheral voltage monitoring 1 enable:

Bits 3:1 PLS[2:0]: Power voltage detector level selection.

Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the

Bit 0 PVDE: Power voltage detector enable

Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR

Power control register 3 (PWR_CR3)

Address offset: 0x08

Reset value: 0x0000 8000 (This register is not reset when exiting Standby modes and with

the PWRRST bit in the RCC_APB1RSTR1 register)

Access: Additional APB cycles are needed to access this register vs. a standard APB

access (3 for a write and 2 for a read).

monitoring vs. 1.62V threshold) disable.

monitoring vs. 1.62V threshold) enable.

monitoring vs. 0.9V threshold) disable.

monitoring vs. 0.9V threshold) enable.

monitoring vs. 1.2V threshold) disable.

monitoring vs. 1.2V threshold) enable.

These bits select the voltage threshold detected by the power voltage detector:

around 2.0 V

around 2.2 V

around 2.4 V

around 2.5 V

around 2.6 V

around 2.8 V

around 2.9 V

111: External input analog voltage PVD_IN (compared internally to VREFINT)

SYSCFG_CBR register.

These bits are reset only by a system reset.

0: Power voltage detector disable.

1: Power voltage detector enable.

This bit is reset only by a system reset.

RM0432 Rev 6

Power control (PWR)

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