ST STM32L4+ Series Reference Manual page 462

Hide thumbs Also See for STM32L4+ Series:

Chrom-GRC™ (GFXMMU)

Graphic MMU status register (GFXMMU_SR)

Address offset: 0x0004

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 AMEF: AHB master error flag

Bit 3 B3OF: Buffer 3 overflow flag

Bit 2 B2OF: Buffer 2 overflow flag

Bit 1 B1OF: Buffer 1 overflow flag

Bit 0 B0OF: Buffer 0 overflow flag

Graphic MMU flag clear register (GFXMMU_FCR)

Address offset: 0x0008

Reset value: 0x0000 0000

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CAMEF: Clear AHB master error flag

Bit 3 CB3OF: Clear buffer 3 overflow flag

This bit is set when an AHB error happens during a transaction. It is cleared by writing 1

This bit is set when an overflow occurs during the offset calculation of the buffer 3. It is

cleared by writing 1 to CB3OF.

This bit is set when an overflow occurs during the offset calculation of the buffer 2. It is

cleared by writing 1 to CB2OF.

This bit is set when an overflow occurs during the offset calculation of the buffer 1. It is

cleared by writing 1 to CB1OF.

This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is

cleared by writing 1 to CB0OF.

Writing 1 clears the AHB master error flag in the GFXMMU_SR register.

Writing 1 clears the buffer 3 overflow flag in the GFXMMU_SR register.

RM0432 Rev 6

Need help?

Do you have a question about the STM32L4+ Series and is the answer not in the manual?