ST STM32L4+ Series Reference Manual page 564

Octo-SPI interface (OCTOSPI)
Double-transfer rate (DTR) mode
Each of the instruction/address/alternate/data phase can be configured to operate in
Double-transfer rate (DTR) mode setting IDTR/ADDTR/ABDTR/DDTR bit in the
OCTOSPI_CCR register.
In Memory-mapped mode, the DTR mode for each phases of the write operations is
specified in the OCTOSPI_WCCR register. The DTR mode for each phases of the read
operations is specified in the regular register (OCTOSPI_CCR).
In DTR mode, when the OCTOSPI drives the IO0/SO, IO1, IO2, IO3, IO4, IO5, IO6 and IO7
signals in the instruction/address/alternate-byte/data phases, a bit is sent or received on
each of the falling and rising edges of CLK.
When receiving data in DTR mode, the OCTOSPI assumes that the external device also
send the data using both CLK rising and falling edges. When DDTR = 1 in OCTOSPI_CCR,
the software must clear SSHIFT in OCTOSPI_TCR. Thus, the signals are sampled one half
of a CLK cycle later (on the following, opposite edge).
In DTR mode, it is recommended to set the delay hold quarter cycle (DHQC) bit of
OCTOSPI_TCR, to shift the outputs by a quarter of cycle and avoid to hold issues on the
memory side.
Note: DHQC must not be set when the prescaler value is 1, as this action leads to unpredictable
behavior.
CS#
CLK
IO[7:0]
Dual-quad mode
When the DQM = 1 in OCTOSPI_CR, the OCTOSPI is in Dual-quad mode: two external
Quad-SPI devices (device A and device B) are used in order to send/receive 8 bits (or
16 bits in DTR mode) every cycle, effectively doubling the throughput as well as the
capacity.
Each device (A or B) uses the same CLK and nCS signals, but each has separate IO0, IO1,
IO2, and IO3 signals.
The Dual-quad mode can be used in conjunction with the Single-bit, Dual-bit, and Quad-bit
modes, as well as with either the SDR or the DTR mode.
The device size, as specified in DEVSIZE[4:0] of OCTOSPI_DCR1, must reflect the total
external device capacity, that is the double of the size of one individual component.
If address X is even, then the byte that the OCTOSPI gives for address X is the byte at the
address X/2 of device A, and the byte that the OCTOSPI gives for address X + 1 is the byte
at the address X/2 of device B. In other words, the bytes at even addresses are all stored in
device A and the bytes at odd addresses are all stored in device B.
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Figure 74. DTR write in Octal mode (Macronix mode) example
02h FDh
RM0432 Rev 6
A[15:8] A[7:0] D1
A[31:24] A[23:16]
Word Unit
RM0432
D0 D255 D254
Word Unit
MSv43491V1