ST STM32L4+ Series Reference Manual page 784

Digital camera interface (DCMI)
24.5.6 DCMI interrupt clear register (DCMI_ICR)
The DCMI_ICR register is write-only. Setting a bit of this register clears the corresponding
flag in the DCMI_RIS and DCMI_MIS registers. Writing 0 has no effect.
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 LINE_ISC: line interrupt status clear
Bit 3 VSYNC_ISC: Vertical Synchronization interrupt status clear
Bit 2 ERR_ISC: Synchronization error interrupt status clear
Note: This bit is available only in embedded synchronization mode.
Bit 1 OVR_ISC: Overrun interrupt status clear
Bit 0 FRAME_ISC: Capture complete interrupt status clear
24.5.7 DCMI embedded synchronization code register (DCMI_ESCR)
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
784/2301
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Setting this bit clears the LINE_RIS flag in the DCMI_RIS register.
Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register.
Setting this bit clears the ERR_RIS flag in the DCMI_RIS register.
Setting this bit clears the OVR_RIS flag in the DCMI_RIS register.
Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register.
28 27 26 25
FEC[7:0]
rw rw rw rw
12 11 10 9
LSC[7:0]
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
24 23 22
rw rw rw
8 7 6
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
LINE VSYNC ERR
Res.
_ISC _ISC _ISC
w w w
21 20 19 18
LEC[7:0]
rw rw rw rw
5 4 3 2
FSC[7:0]
rw rw rw rw
RM0432
17 16
Res. Res.
1 0
OVR FRAME
_ISC _ISC
w w
17 16
rw rw
1 0
rw rw