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RM0432
Bits 7: 2 Reserved, must be kept at reset value
Bits 1: 0 NL: Number of Lanes
30.15.38 DSI Host PHY ULPS Control Register (DSI_PUCR)
Address offset: 0x00A8
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31: 4 Reserved, must be kept at reset value
Bit 3 UEDL: ULPS Exit on Data Lane
Bit 2 URDL: ULPS Request on Data Lane
Bit 1 UECL: ULPS Exit on Clock Lane
Bit 0 URCL: ULPS Request on Clock Lane
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
This field configures the number of active data lanes:
00: One data lane (lane 0)
01: Two data lanes (lanes 0 and 1) - Reset value
10: Reserved
11: Reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
ULPS mode Exit on all active data lanes.
0: No exit request
1: Exit ULPS mode on all active data lane URDL
ULPS mode Request on all active data lanes.
0: No ULPS request
1: Request ULPS mode on all active data lane UECL
ULPS mode Exit on clock lane.
0: No exit request
1: Exit ULPS mode on clock lane
ULPS mode Request on clock lane.
0: No ULPS request
1: Request ULPS mode on clock lane
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
UEDL
URDL
rw
rw
17
16
Res.
Res.
1
0
UECL
URCL
rw
rw
1007/2301
1044
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