ST STM32L4+ Series Reference Manual page 767

RM0432
24.3.1 DCMI block diagram
Figure 167
24.3.2 DCMI pins
The following table shows DCMI pins.
Mode
8 bits
10 bits
12 bits
14 bits
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
24.3.3 DCMI clocks
The digital camera interface uses two clock domains, DCMI_PIXCLK and HCLK. The
signals generated with DCMI_PIXCLK are sampled on the rising edge of HCLK once they
are stable. An enable signal is generated in the HCLK domain, to indicate that data coming
shows the DCMI block diagram.
Figure 167. DCMI block diagram
DMA
interface
AHB
interface
FIFO
Data
formatter
Figure 168. Top-level block diagram
HCLK
Interrupt DCMI_IT
controller
DMA_REQ
Table 154. DCMI input/output pins
Pin name Signal type
DCMI_D[7:0]
DCMI_D[9:0]
Inputs
DCMI_D[11:0]
DCMI_D[13:0]
Input
Input
Input
Control/Statusregister
Data Synchronizer
extraction
DCMI_D[13:0], DCMI_HSYNC, DCMI_VSYNC
DCMI
DCMI data
Pixel clock
Horizontal synchronization / Data valid
Vertical synchronization
RM0432 Rev 6
Digital camera interface (DCMI)
DCMI_PIXCLK
DCMI_D[13:0]
DCMI_PIXCLK
External
interface
DCMI_HSYNC
DCMI_VSYNC
Description
ai5604c
ai15603c
767/2301
789