ST STM32L4+ Series Reference Manual page 508

Flexible static memory controller (FSMC)
A[25:0]
NBL[x:0]
NEx
NOE
NWE
Data bus
The DATAHLD time at the end of the read and write transactions guarantee the address and
data hold time after the NOE/NWE rising edge. The DATAST value must be greater than
zero (DATAST > 0).
Bit number
31:24
23:22
21
20
19
18:16
15
14
13
12
11
10
9
8
7
508/2301
Figure 49. Mode 1 write access waveforms
NBLSET ADDSET HCLK cycles
HCLK
cycles
Table 93. FMC_BCRx bitfields (mode 1)
Bit name
Reserved 0x000
NBLSET[1:0] As needed
WFDIS As needed
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x0
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
Reserved 0x0
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
RM0432 Rev 6
Memory transaction
Data driven by controller
DATAST HCLK cycles
Value to set
RM0432
DATAHLD +1
HCLK cycles
MSv41665V1