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System configuration controller (SYSCFG)
Bits 11:8 EXTI14[3:0]: EXTI 14 configuration bits
Bits 7:4 EXTI13[3:0]: EXTI 13 configuration bits
Bits 3:0 EXTI12[3:0]: EXTI 12 configuration bits
Note:
Some of the I/O pins mentioned in the above register may not be available on small
packages.
9.2.7
SYSCFG SRAM2 control and status register (SYSCFG_SCSR)
Address offset: 0x18
System reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
360/2301
These bits are written by software to select the source input for the EXTI14 external
interrupt.
0000: PA[14] pin
0001: PB[14] pin
0010: PC[14] pin
0011: PD[14] pin
0100: PE[14] pin
0101: PF[14] pin
0110: PG[14] pin
0111: PH[14] pin
1000: Reserved
These bits are written by software to select the source input for the EXTI13 external
interrupt.
0000: PA[13] pin
0001: PB[13] pin
0010: PC[13] pin
0011: PD[13] pin
0100: PE[13] pin
0101: PF[13] pin
0110: PG[13] pin
0111: PH[13] pin
1000: Reserved
These bits are written by software to select the source input for the EXTI12 external
interrupt.
0000: PA[12] pin
0001: PB[12] pin
0010: PC[12] pin
0011: PD[12] pin
0100: PE[12] pin
0101: PF[12] pin
0110: PG[12] pin
0111: PH[12] pin
1000: Reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0432
17
16
Res.
Res.
1
0
SRAM2
SRAM2
BSY
ER
r
rw
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