ST STM32L4+ Series Reference Manual page 891

RM0432
29.4 LTDC functional description
29.4.1 LTDC block diagram
The block diagram of the LTDC is shown in the figure below.
Interrupts
Layer FIFO: One FIFO 64x32-bit per layer.
PFC: pixel format converter, performing the pixel format conversion from the selected input
pixel format of a layer to words.
AHB interface: for data transfer from memories to the FIFO.
Blending, dithering unit and timings generator: Refer to
29.4.2 LTDC pins and external signal interface
The table below summarizes the LTDC signal interface.
LCD-TFT signals
LCD_CLK
LCD_HSYNC
LCD_VSYNC
LCD_DE
LCD_R[7:0]
LCD_G[7:0]
LCD_B[7:0]
Figure 199. LTDC block diagram
Pixel clock domain
Layer1
FIFO
AHB
interface
Layer1
FIFO
Configuration
Timing
and status
generator
registers
Table 193. LTDC pins and signal interface
I/O
O
O
O
O
O
O
O
RM0432 Rev 6
LCD-TFT display controller (LTDC)
PFC
Dithering
Blending
unit
unit
PFC
Section 29.5.1
Clock output
Horizontal synchronization
Vertical synchronization
Not data enable
Data: 8-bit red data
Data: 8-bit green data
Data: 8-bit blue data
LCD_HSYNC
LCD_VSYNC
LCD_DE
LCD_CLK
LCD_R[7:0]
LCD_G[7:0]
LCD_B[7:0]
and Section
Description
LCD-TFT
panel
MSv19675V1
29.5.2.
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