RM0432
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset, or unless a
failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 32 used as RTC clock
Bit 7 LSESYSDIS: Disable the Clock LSE propagation to the system
Set by software to disable the Clock LSE propagation to the system. Only RTC is clocked by
LSE when this bit is set.
1: No clock LSE propagation
0: Clock LSE propagation enabled
Note: This bit is available only on STM32L4P5xx and STM32L4Q5xx.
Bit 6 LSECSSD: CSS on LSE failure detection
Set by hardware to indicate when a failure has been detected by the clock security system
on the external 32 kHz oscillator (LSE).
0: No failure detected on LSE (32 kHz oscillator)
1: Failure detected on LSE (32 kHz oscillator)
Bit 5 LSECSSON: CSS on LSE enable
Set by software to enable the Clock Security System on LSE (32 kHz oscillator).
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and
ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected and LSIPREDIV
(see note below) is disabled.
Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD
=1). In that case the software MUST disable the LSECSSON bit.
0: CSS on LSE (32 kHz external oscillator) OFF
1: CSS on LSE (32 kHz external oscillator) ON
Note: LSIPREDIV bit is available only on STM32L5P5xx and STM32L4Q5xx.
Bits 4:3 LSEDRV[1:0] LSE oscillator drive capability
Set by software to modulate the LSE oscillator's drive capability.
00: 'Xtal mode' lower driving capability
01: 'Xtal mode' medium low driving capability
10: 'Xtal mode' medium high driving capability
11: 'Xtal mode' higher driving capability
The oscillator is in Xtal mode when it is not in bypass mode.
RM0432 Rev 6
Reset and clock control (RCC)
309/2301
320
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