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LCD-TFT display controller (LTDC)
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 BCRED[7:0]: background color red value
These bits configure the background red value.
Bits 15:8 BCGREEN[7:0]: background color green value
These bits configure the background green value.
Bits 7:0 BCBLUE[7:0]: background color blue value
These bits configure the background blue value.
29.8.8
LTDC interrupt enable register (LTDC_IER)
This register determines which status flags generate an interrupt request by setting the
corresponding bit to 1.
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 RRIE: register reload interrupt enable
This bit is set and cleared by software.
0: register reload interrupt disable
1: register reload interrupt enable
Bit 2 TERRIE: transfer error interrupt enable
This bit is set and cleared by software.
0: transfer error interrupt disable
1: transfer error interrupt enable
Bit 1 FUIE: FIFO underrun interrupt enable
This bit is set and cleared by software.
0: FIFO underrun interrupt disable
1: FIFO underrun Interrupt enable
Bit 0 LIE: line interrupt enable
This bit is set and cleared by software.
0: line interrupt disable
1: line interrupt enable
908/2301
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0432 Rev 6
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
RM0432
19
18
17
Res.
Res.
Res.
Res.
3
2
1
RRIE
TERRIE
FUIE
LIE
rw
rw
rw
16
0
rw
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