ST STM32L4+ Series Reference Manual page 574

Octo-SPI interface (OCTOSPI)
after a period defined by TIMEOUT[15:0] in OCTOSPI_LPTR, when x cycles have elapsed
without an access since the clock is inactive.
BUSY goes high as soon as the first memory-mapped access occurs. Because of the
prefetch operations, BUSY does not fall until there is an abort, or the peripheral is disabled.
19.4.11 OCTOSPI configuration introduction
The OCTOSPI configuration is done in three steps:
1. OCTOSPI system configuration
2. OCTOSPI device configuration
3. OCTOSPI mode configuration
19.4.12 OCTOSPI system configuration
The OCTOSPI is configured using the OCTOSPI_CR. The user must program:
• Functional mode with FMODE[1:0]
•
Polling mode behavior if needed with PMM and APMS bits
• FIFO level with FTHRES[4:0]
•
DMA usage with DMAEN
• Timeout counter usage with TCEN
•
Dual-quad mode, if needed, with DQM (only for Quad-SPI configuration)
In case of an interrupt usage, the respective enable bit can also be set during this phase.
If the timeout counter is used, the timeout value is programmed in OCTOSPI_LPTR.
The DMA channel must not be enabled during the OCTOSPI configuration: it must be
enabled only when the operation is fully configured, to avoid any unexpected request
generation.
The DMA and OCTOSPI must be configured in a coherent manner regarding data length:
the FTHRES[4:0] value in OCTOSPI must reflect the DMA burst size.
19.4.13 OCTOSPI device configuration
The parameters related to the external device targeted are configured through
OCTOSPI_DCR1 and OCTOSPI_DCR2.The user must program:
•
Device size with DEVSIZE[4:0]
•
Chip-select minimum high time with CSHT[5:0]
•
Clock mode with FRCK and CKMODE
•
Device frequency with PRESCALER[7:0]
MTYP[2:0] defines the memory type to be used for 8-line modes:
•
Micron mode with D0/D1 ordering in 8-data-bit mode (DMODE[2:0] = 100)
•
Macronix mode with D1/D0 ordering in 8-data-bit mode (DMODE[2:0] = 100)
•
HyperBus memory mode: the protocol follows the HyperBus specification, and an 8-
data-bit DDR mode must be selected.
• HyperBus register mode, addressing register space: the memory-mapped accesses in
this mode must be non-cacheable, or the indirect read/write modes must be used.
574/2301 RM0432 Rev 6
RM0432