ST STM32L4+ Series Reference Manual page 846

Digital filter for sigma delta modulators (DFSDM)
the final output sample (and next samples) from filter will be calculated from later input data.
This final sample then looks a bit in forward - because it is calculated from newer input
samples than the "non-skipped" sample. The final "skipped sample" is converted later
because the skipped input data samples must be replaced by followed input data samples.
The final data buffers behavior (skipped and non-skipped output data buffers comparison)
looks like the non-skipped data stream is a bit delayed - both data buffers will be phase
shifted.
Number of clock pulses to be skipped should be written into PLSSKP[5:0] field in
DFSDM_CHyDLYR register. Once PLSSKP[5:0] field is written the execution of pulses
skipping is started on given channel. PLSSKP[5:0] field can be read in order to check the
progress of pulses skipper. When PLSSKP[5:0]=0 means that pulses skipping has been
executed.
Up to 63 clock pulses can be skip with a single write operation into PLSSKP[5:0]. If more
pulses need to be skipped, then user has to write several times into the PLSSKP[5:0] field.
The application software should handle cumulative skipped clock number per each filter.
28.4.5 Configuring the input serial interface
The following parameters must be configured for the input serial interface:
•
Output clock predivider. There is a programmable predivider to generate the output
clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in
DFSDM_CH0CFGR1 register.
•
Serial interface type and input clock phase. Selection of SPI or Manchester coding
and sampling edge of input clock. It is defined by SITP [1:0] bits in
DFSDM_CHyCFGR1 register.
•
Input clock source. External source from CKINy pin or internal from CKOUT pin. It is
defined by SPICKSEL[1:0] field in DFSDM_CHyCFGR1 register.
•
Final data right bit-shift. Defines the final data right bit shift to have the result aligned
to a 24-bit value. It is defined by DTRBS[4:0] in DFSDM_CHyCFGR2 register.
•
Channel offset per channel. Defines the analog offset of a given serial channel (offset
of connected external Σ∆ modulator). It is defined by OFFSET[23:0] bits in
DFSDM_CHyCFGR2 register.
•
short-circuit detector and clock absence per channel enable. To enable or disable
the short-circuit detector (by SCDEN bit) and the clock absence monitoring (by
CKABEN bit) on a given serial channel in register DFSDM_CHyCFGR1.
•
Analog watchdog filter and short-circuit detector threshold settings. To configure
channel analog watchdog filter parameters and channel short-circuit detector
parameters. Configurations are defined in DFSDM_CHyAWSCDR register.
28.4.6 Parallel data inputs
Each input channel provides a register for 16-bit parallel data input (besides serial data
input). Each 16-bit parallel input can be sourced from internal data sources only:
•
internal ADC results
•
direct CPU/DMA writing.
The selection for using serial or parallel data input for a given channel is done by field
DATMPX[1:0] of DFSDM_CHyCFGR1 register. In DATMPX[1:0] is also defined the parallel
data source: internal ADC or direct write by CPU/DMA.
846/2301 RM0432 Rev 6
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