ST STM32L4+ Series Reference Manual page 126

Embedded Flash memory (FLASH)
a write/erase operation is performed to the other bank (refer to
write (RWW) available only in Dual-bank mode
programming is only possible in the voltage scaling range 1. The VOS[1:0] bits in the
PWR_CR1 must be programmed to 01b.
On the contrary, during a program/erase operation to the Flash memory, any attempt to read
the same Flash memory bank will stall the bus. The read operation will proceed correctly
once the program/erase operation has completed.
Unlocking the Flash memory
After reset, write is not allowed in the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1. Write KEY1 = 0x45670123 in the
2. Write KEY2 = 0xCDEF89AB in the FLASH_KEYR register.
Any wrong sequence will lock up the FLASH_CR register until the next system reset. In the
case of a wrong key sequence, a bus error is detected and a Hard Fault interrupt is
generated.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
Note: The FLASH_CR register cannot be written when the BSY bit in the
(FLASH_SR)
stall until the BSY bit is cleared.
3.3.6 Flash main memory erase sequences
The Flash memory erase operation can be performed at page level, bank level or on the
whole Flash memory (Mass Erase). Mass Erase does not affect the Information block
(system Flash, OTP and option bytes).
Page erase
To erase a page, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
status register
2. Check and clear all error programming flags due to a previous programming. If not,
PGSERR is set.
3. In Dual-bank mode (DBANK option bit is set), set the PER bit and select the page to
erase (PNB) with the associated bank (BKER) in the Flash control register
(FLASH_CR). In Single-bank mode (DBANK option bit is reset), set the PER bit and
select the page to erase (PNB). The BKER bit in the Flash control register
(FLASH_CR) must be kept cleared.
4. Set the STRT bit in the FLASH_CR register.
5. Wait for the BSY bit to be cleared in the FLASH_SR register.
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when STRT bit is set, and
disabled automatically when STRT bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.
If the page erase is part of write-protected area (by WRP or PCROP), WRPERR is set and
the page erase request is aborted.
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is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to
(FLASH_SR).
RM0432 Rev 6
(DBANK=1)). The Flash erase and
Flash control register (FLASH_CR)
Flash key register (FLASH_KEYR)
RM0432
Section 3.3.8: Read-while-
to protect the
Flash status register
Flash