ST STM32L4+ Series Reference Manual page 328

Clock recovery system (CRS)
Bits 26:24 SYNCDIV[2:0]: SYNC divider
Bits 23:16 FELIM[7:0]: Frequency error limit
Bits 15:0 RELOAD[15:0]: Counter reload value
7.7.3 CRS interrupt and status register (CRS_ISR)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
r r r
15 14 13 12
FEDIR Res. Res. Res.
r
Bits 31:16 FECAP[15:0]: Frequency error capture
Bit 15 FEDIR: Frequency error direction
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 TRIMOVF: Trimming overflow or underflow
328/2301
These bits are set and cleared by software to control the division factor of the SYNC signal.
000: SYNC not divided (default)
001: SYNC divided by 2
010: SYNC divided by 4
011: SYNC divided by 8
100: SYNC divided by 16
101: SYNC divided by 32
110: SYNC divided by 64
111: SYNC divided by 128
FELIM contains the value to be used to evaluate the captured frequency error value latched
in the FECAP[15:0] bits of the CRS_ISR register. Refer to
about FECAP evaluation.
RELOAD is the value to be loaded in the frequency error counter with each SYNC event.
Refer to Section 7.4.3 for more details about counter behavior.
27 26 25
r r r r
11 10 9
TRIM SYNC
Res.
OVF MISS
r r
FECAP is the frequency error counter value latched in the time of the last SYNC event.
Refer to Section 7.4.4 for more details about FECAP usage.
FEDIR is the counting direction of the frequency error counter latched in the time of the last
SYNC event. It shows whether the actual frequency is below or above the target.
0: Upcounting direction, the actual frequency is above the target.
1: Downcounting direction, the actual frequency is below the target.
This flag is set by hardware when the automatic trimming tries to over- or under-flow the
TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is
cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No trimming error signalized
1: Trimming error signalized
24 23 22 21
FECAP[15:0]
r r r r
8 7 6 5
SYNC
Res. Res. Res.
ERR
r
RM0432 Rev 6
Section 7.4.4 for more details
20 19 18
r r r
4 3 2
SYNC
Res. ESYNCF ERRF
WARNF
r r
RM0432
17 16
r r
1 0
SYNC
OKF
r r