ST STM32L4+ Series Reference Manual page 1035

RM0432
Bits 31: 27 Reserved
Bits 26:25 LPRXFT: Low-Power RX low-pass Filtering Tuning
Bits 24: 23 Reserved
Bit 22 FLPRXLPM: Forces LP Receiver in Low-Power mode
Bits 21: 20 Reserved
Bits 19:18 HSTXSRCDL: High-Speed Transmission Slew Rate Control on Data Lanes
Bits 17:16 HSTXSRCCL: High-Speed Transmission Slew Rate Control on Clock Lane
Bits 15:13 Reserved
Bit 12 SDDC: SDD Control
Bits 11: 10 Reserved
Bits 9:8 LPSRCDL: Low-Power transmission Slew Rate Compensation on Data Lanes
Bits 7:6 LPSRCCL: Low-Power transmission Slew Rate Compensation on Clock Lane
Bits 5: 4 Reserved
Bits 3:2 HSTXDDL: High-Speed Transmission Delay on Data Lanes
Bits 1:0 HSTXDCL: High-Speed Transmission Delay on Clock Lane
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
This signal can be used to tune the cutoff frequency of low-pass filter at the input of LPRX.
This bit enables the Low-Power mode of LP receiver (LPRX). When set, the LPRX
operates in Low-Power mode all the time (when this is not activated, LPRX operates in
Low-Power mode during ULPS only):
0: No effect.
1: LPRX is forced in Low-Power mode.
Slewrate Control for High Speed Transmitter Output. It can be used to change slew rate of
Data lane HS transitions.
Default value should be '00'.
Slewrate Control for High Speed Transmitter Output. It can be used to change slew rate of
Clock lane HS transitions.
Default value should be '00'.
Switch on the additional current path to meet the SDDTx parameter defined by MIPI
PHY Specification on both clock and data lanes.
0: No effect.
1: Activate additional current path on all lanes.
Can be used to change slew rate of Data lane LP transitions.
Default value should be '00'.
Can be used to change slew rate of Clock lane LP transitions.
Default value should be '00'.
Delay tuner control to change delay (up to DP/DN) in data path. Can be used to change
data edge transition positions with respect to clock edge on DP/DN.
Default value should be '00'.
Delay tuner control to change delay (upto DP/DN) in clock path. Can be used to change
clock edge position with respect to data bit transitions on DP/DN.
Default value should be '00'.
RM0432 Rev 6
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D-
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