ST STM32L4+ Series Reference Manual page 472

Nested vectored interrupt controller (NVIC)
Table 76. STM32L4Rxxx and STM32L4Sxxx vector table (continued)
Type of
priority
76 83 settable
77 84 settable
78 85 settable
79 86 settable
80 87 settable
81 88 settable
82 89 settable
83 90 settable
84 91 settable
85 92 settable
86 93 settable
87 94 settable
88 95 settable
89 96 settable
90 97 settable
91 98 settable
92 99 settable
93 100 settable
94 101 settable
Type of
priority
- - -
- -3 fixed
- -2 fixed
472/2301
Acronym
OCTOSPI2
TSC
DSIHSOT
AES
RNG
FPU
HASH and CRS
I2C4_ER
I2C4_EV
DCMI
Reserved
Reserved
Reserved
Reserved
DMA2D
LCD-TFT
LCD-TFT_ER
GFXMMU
DMAMUX1_OVR
Table 77. STM32L4P5xx and STM32Q5xx vector table
Acronym
-
Reset
NMI
Description
OCTOSPI2 global interrupt
TSC global interrupt
DSI global interrupt
AES global interrupt
RNG global interrupt
Floating point interrupt
HASH and CRS interrupt
I2C4 error interrupt
I2C4 event interrupt
DCMI global interrupt
Reserved
Reserved
Reserved
Reserved
DMA2D global interrupt
LTDC global interrupt
LTDC global error interrupt
GFXMMU global error interrupt
DMAMUX Overrun interrupt
Description
Reserved
Reset
Non maskable interrupt. The RCC Clock
Security System (CSS) is linked to the NMI
vector.
RM0432 Rev 6
RM0432
Address
0x0000 0170
0x0000 0174
0x0000 0178
0x0000 017C
0x0000 0180
0x0000 0184
0x0000 0188
0x0000 018C
0x0000 0190
0x0000 0194
0x0000 0198
0x0000 019C
0x0000 01A0
0x0000 01A4
0x0000 01A8
0x0000 019C
0x0000 01A0
0x0000 01A4
0x0000 01A8
Address
0x0000 0000
0x0000 0004
0x0000 0008