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Reset and clock control (RCC)
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear
Bit 9 LSECSSC: LSE Clock security system interrupt clear
Bit 8 CSSC: Clock security system interrupt clear
Bit 7 PLLSAI2RDYC: PLLSAI2 ready interrupt clear
Bit 6 PLLSAI1RDYC: PLLSAI1 ready interrupt clear
Bit 5 PLLRDYC: PLL ready interrupt clear
Bit 4 HSERDYC: HSE ready interrupt clear
Bit 3 HSIRDYC: HSI16 ready interrupt clear
276/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
HSI48
LSECS
Res.
RDYC
SC
w
This bit is set by software to clear the HSI48RDYF flag.
0: No effect
1: Clear the HSI48RDYC flag
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
This bit is set by software to clear the PLLSAI2RDYF flag.
0: No effect
1: Clear PLLSAI2RDYF flag
This bit is set by software to clear the PLLSAI1RDYF flag.
0: No effect
1: Clear PLLSAI1RDYF flag
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
24
23
22
Res.
Res.
Res.
Res.
8
7
6
PLLSAI
PLLSAI
CSSC
2RDYC
1RDYC
RDYC
w
w
w
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PLL
HSER
HSIRD
MSIRD
DYC
YC
YC
w
w
w
w
RM0432
17
16
Res.
Res.
1
0
LSERD
LSIRDY
YC
C
w
w
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