ST STM32L4+ Series Reference Manual page 222

Power control (PWR)
Bit 4 WP5: Wakeup pin WKUP5 polarity
Bit 3 WP4: Wakeup pin WKUP4 polarity
Bit 2 WP3: Wakeup pin WKUP3 polarity
Bit 1 WP2: Wakeup pin WKUP2 polarity
Bit 0 WP1: Wakeup pin WKUP1 polarity
5.4.5 Power status register 1 ( PWR_SR1 )
Address offset: 0x10
Reset value: 0x0000 0000 (This register is not reset when exiting Standby modes and with
the PWRRST bit in the RCC_APB1RSTR1 register)
Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.
31 30 29
Res. Res. Res. Res.
15 14 13
EXT_S
WUFI Res. MPS_R Res.
DY
r r
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 WUFI: Wakeup flag internal
Bit 14 Reserved, must be kept at reset value.
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This bit defines the polarity used for an event detection on external wake-up pin, WKUP5
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP4
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all
internal wakeup sources are cleared.
24 23 22
Res. Res. Res.
8 7 6
SBF Res. Res.
r
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. WUF5 WUF4 WUF3
r r r
RM0432
17 16
Res. Res.
1 0
WUF2 WUF1
r r