Advertisement
Digital-to-analog converter (DAC)
22.7.13
DAC channel2 data output register (DAC_DOR2)
This register is available only on dual-channel DACs. Refer to
implementation.
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
22.7.14
DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
CAL_
DMAU
BWST2
Res.
FLAG2
DR2
r
r
rc_w1
15
14
13
CAL_
DMAU
BWST1
Res.
FLAG1
DR1
r
r
rc_w1
754/2301
27
26
25
Res.
Res.
Res.
11
10
9
r
r
r
These bits are read-only, they contain data output for DAC channel2.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
DACC2DOR[11:0]
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
Section 22.3: DAC
21
20
19
18
Res.
Res.
Res.
5
4
3
2
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0432
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
Res.
Res.
Advertisement
Need help?
Do you have a question about the STM32L4+ Series and is the answer not in the manual?