ST STM32L4+ Series Reference Manual page 1060

Touch sensing controller (TSC)
31.6.8 TSC I/O channel control register (TSC_IOCCR)
Address offset: 0x28
Reset value: 0x0000 0000
31 30 29
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw
15 14 13
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw
Bits 31:0 Gx_IOy: Gx_IOy channel mode
These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
0: Gx_IOy unused
1: Gx_IOy used as channel
Note: These bits must not be modified when an acquisition is ongoing.
31.6.9 TSC I/O group control status register (TSC_IOGCSR)
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 GxS: Analog I/O group x status
Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 GxE: Analog I/O group x enable
1060/2301
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
These bits are set by hardware when the acquisition on the corresponding enabled analog
I/O group x is complete. They are cleared by hardware when a new acquisition is started.
0: Acquisition on analog I/O group x is ongoing or not started
1: Acquisition on analog I/O group x is complete
groups are not set.
These bits are set and cleared by software to enable/disable the acquisition (counter is
counting) on the corresponding analog I/O group x.
0: Acquisition on analog I/O group x disabled
1: Acquisition on analog I/O group x enabled
24 23 22
rw rw rw
8 7 6
rw rw rw
24 23 22
Res. G8S G7S
r r
8 7 6
Res. G8E G7E
rw rw
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
G6S G5S G4S G3S
r r r r
5 4 3 2
G6E G5E G4E G3E
rw rw rw rw
RM0432
17 16
rw rw
1 0
rw rw
17 16
G2S G1S
r r
1 0
G2E G1E
rw rw