ST STM32L4+ Series Reference Manual page 122

Embedded Flash memory (FLASH)
Table 12. Number of wait states according to CPU clock (HCLK) frequency
Wait states (WS)
0 WS (1 CPU cycles)
1 WS (2 CPU cycles)
2 WS (3 CPU cycles)
3 WS (4 CPU cycles)
4 WS (5 CPU cycles)
5 WS (6 CPU cycles)
After reset, the CPU clock frequency is 4 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
When changing the CPU frequency, the following software sequences must be applied in
order to tune the number of wait states needed to access the Flash memory:
Increasing the CPU frequency:
1. Program the new number of wait states to the LATENCY bits in the
control register
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register.
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Decreasing the CPU frequency:
1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
4. Program the new number of wait states to the LATENCY bits in
register
5. Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register.
3.3.4 Adaptive real-time memory accelerator (ART Accelerator
The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard Arm
performance advantage of the Arm
technologies, which normally requires the processor to wait for the Flash memory at higher
operating frequencies.
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(Latency)
(FLASH_ACR).
(FLASH_ACR).
® ®
Cortex -M4 with FPU processors. It balances the inherent
V Range 1
CORE
≤20
≤40
≤60
≤80
≤100
≤120
® ®
Cortex -M4 with FPU over Flash memory
RM0432 Rev 6
HCLK (MHz)
V Range 2
CORE
≤8
≤16
≤26
-
-
-
Flash access
Flash access control
RM0432