ST STM32L4+ Series Reference Manual page 584

Octo-SPI interface (OCTOSPI)
Bit 7 FSEL: Flash select
This bit selects the Flash memory to be addressed in Single/Dual/Quad mode in Single-Flash
mode (when DQM = 0).
0: FLASH 1 selected (data exchanged over IO[3:0])
1: FLASH 2 selected (data exchanged over IO[7:4])
This bit is ignored when DQM = 1 or when Octal mode is selected.
This bit can be modified only when BUSY = 0.
Bit 6 DQM: Dual-quad mode
This bit activates the Dual-quad mode, where two external devices are used simultaneously
to double the throughput and the capacity
0: Dual-quad mode disabled
1: Dual-quad mode enabled
This bit can be modified only when BUSY = 0.
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 TCEN: Timeout counter enable
This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit
enables the timeout counter.
0: Timeout counter is disabled, and thus the chip-select (nCS) remains active indefinitely
after an access in Memory-mapped mode.
1: Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped
mode after TIMEOUT[15:0] cycles of external device inactivity.
This bit can be modified only when BUSY = 0.
Bit 2 DMAEN: DMA enable
In Indirect mode, the DMA can be used to input or output data via OCTOSPI_DR. DMA
transfers are initiated when FTF is set.
0: DMA disabled for Indirect mode
1: DMA enabled for Indirect mode
Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with
Bit 1 ABORT: Abort request
This bit aborts the on-going command sequence. It is automatically reset once the abort is
completed. This bit stops the current transfer.
0: No abort requested
1: Abort requested
Note: This bit is always read as 0.
Bit 0 EN: Enable
This bit enables the OCTOSPI.
0: OCTOSPI disabled
1: OCTOSPI enabled
Note: The DMA request may be aborted without having received the ACK. In this case, the EN
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the DMA. Do not write this bit during DMA operation.
bit is cleared during the operation.
RM0432 Rev 6
RM0432