ST STM32L4+ Series Reference Manual page 690

Analog-to-digital converters (ADC)
21.6 ADC registers (for each ADC)
Refer to
21.6.1 ADC interrupt and status register (ADC_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 JQOVF: Injected context queue overflow
This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared
by software writing 1 to it. Refer to
more information.
0: No injected context queue overflow occurred (or the flag event was already acknowledged and
cleared by software)
1: Injected context queue overflow has occurred
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.
0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 3 event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.
0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 2 event occurred
Bit 7 AWD1: Analog watchdog 1 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.
0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 1 event occurred
Bit 6 JEOS: Injected channel end of sequence flag
This bit is set by hardware at the end of the conversions of all injected channels in the group. It is
cleared by software writing 1 to it.
0: Injected conversion sequence not complete (or the flag event was already acknowledged and
cleared by software)
1: Injected conversions complete
690/2301
Section 1.2 on page 84
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. JQOVF AWD3
rc_w1 rc_w1
for a list of abbreviations used in register descriptions.
24 23 22
Res. Res. Res. Res.
8 7 6
AWD2 AWD1 JEOS JEOC
rc_w1 rc_w1 rc_w1 rc_w1
Section 21.4.21: Queue of context for injected conversions
RM0432 Rev 6
21 20 19 18
Res. Res. Res.
5 4 3 2
OVR EOS EOC
rc_w1 rc_w1 rc_w1
RM0432
17 16
Res. Res.
1 0
EOSMP ADRDY
rc_w1 rc_w1
for