ST STM32L4+ Series Reference Manual page 550

Flexible static memory controller (FSMC)
Bit 0 IRS: Interrupt rising edge status
The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
Note: If this bit is written by software to 1 it is set.
Common memory space timing register (FMC_PMEM)
Address offset: Address: 0x88
Reset value: 0xFCFC FCFC
The FMC_PMEM read/write register contains the timing information for NAND Flash
memory bank. This information is used to access either the common memory space of the
NAND Flash for command, address write access and data read/write access.
31 30 29
rw rw rw
15 14 13
MEMWAIT[7:0]
rw rw rw
Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time
Bits 23:16 MEMHOLD[7:0]: Common memory hold time
Bits 15:8 MEMWAIT[7:0]: Common memory wait time
550/2301
28 27 26 25
MEMHIZ[7:0]
rw rw rw rw
12 11 10 9
rw rw rw rw
Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the
start of a NAND Flash write access to common memory space on socket. This is only valid
for write transactions:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for
read access during which the address is held (and data for write accesses) after the
command is deasserted (NWE, NOE), for NAND Flash read or write access to common
memory space on socket x:
0000 0000: reserved.
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: reserved.
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for NAND Flash read or write access to common memory space on socket. The
duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.
24 23 22
rw rw rw
8 7 6
rw rw rw
RM0432 Rev 6
21 20 19 18
MEMHOLD[7:0]
rw rw rw rw
5 4 3 2
MEMSET[7:0]
rw rw rw rw
RM0432
17 16
rw rw
1 0
rw rw