ST STM32L4+ Series Reference Manual page 1095

RM0432
34.3 AES implementation
The devices have one AES peripheral. On STM32L4Pxx and STM32L4Qxx, the
AES_KEYRx registers are write-only.
34.4 AES functional description
34.4.1 AES block diagram
Figure 252
32-bit
AHB bus
aes_hclk
aes_in_dma
aes_out_dma
34.4.2 AES internal signals
Table 225
Signal name
aes_hclk
aes_it
aes_in_dma
aes_out_dma
shows the block diagram of AES.
Figure 252. AES block diagram
AES
AHB
interface
DMA
interface
IRQ
aes_it
interface
describes the user relevant internal signals interfacing the AES peripheral.
Table 225. AES internal input/output signals
Signal type
Input
Output
Input/Output
Input/Output
32-bit
Banked registers
access
AES_KEYRx
key
IV, counter AES_IVRx
status AES_SR
AES_CR
control
AES_DINR
data in
AES_DOUTR
data out
AES_SUSPRx
Control Logic
AHB bus clock
AES interrupt request
Input DMA single request/acknowledge
Output DMA single request/acknowledge
RM0432 Rev 6
AES hardware accelerator (AES)
KEY
IVI
swap
AES
DIN Core
(AEA)
DOUT
Save / Restore
Description
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